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frontend/bist: cleanup the way we expose signals for debugging

This commit is contained in:
Florent Kermarrec 2016-12-17 18:44:36 +01:00
parent c090593e52
commit a613c49783
1 changed files with 13 additions and 24 deletions
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37
litedram/frontend/bist.py
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@ -86,11 +86,9 @@ class _LiteDRAMBISTGenerator(Module):
gen_cls = LFSR if random else Counter gen_cls = LFSR if random else Counter
self.submodules.gen = gen = gen_cls(dram_port.dw) self.submodules.gen = gen = gen_cls(dram_port.dw)
cmd_counter = Signal(dram_port.aw) self.cmd_counter = cmd_counter = Signal(dram_port.aw)
fsm = FSM(reset_state="IDLE")
self.submodules += fsm
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE", fsm.act("IDLE",
If(self.start, If(self.start,
NextValue(cmd_counter, 0), NextValue(cmd_counter, 0),
@ -149,7 +147,7 @@ class LiteDRAMBISTGenerator(Module, AutoCSR):
core = ResetInserter()(_LiteDRAMBISTGenerator(dram_port, random)) core = ResetInserter()(_LiteDRAMBISTGenerator(dram_port, random))
self.submodules.core = ClockDomainsRenamer(cd)(core) self.submodules.core = ClockDomainsRenamer(cd)(core)
reset_sync = BusSynchronizer(1, "sys", cd) reset_sync = PulseSynchronizer("sys", cd)
start_sync = PulseSynchronizer("sys", cd) start_sync = PulseSynchronizer("sys", cd)
self.submodules += reset_sync, start_sync self.submodules += reset_sync, start_sync
self.comb += [ self.comb += [
@ -197,9 +195,8 @@ class _LiteDRAMBISTChecker(Module, AutoCSR):
self.submodules.gen = gen = gen_cls(dram_port.dw) self.submodules.gen = gen = gen_cls(dram_port.dw)
# address # address
self._cmd_counter = cmd_counter = Signal(dram_port.aw) self.cmd_counter = cmd_counter = Signal(dram_port.aw)
cmd_fsm = FSM(reset_state="IDLE") self.submodules.cmd_fsm = cmd_fsm = FSM(reset_state="IDLE")
self.submodules += cmd_fsm
cmd_fsm.act("IDLE", cmd_fsm.act("IDLE",
If(self.start, If(self.start,
@ -220,18 +217,11 @@ class _LiteDRAMBISTChecker(Module, AutoCSR):
self.comb += dma.sink.address.eq(self.base + cmd_counter) self.comb += dma.sink.address.eq(self.base + cmd_counter)
# data # data
self._data_counter = data_counter = Signal(dram_port.aw) self.data_counter = data_counter = Signal(dram_port.aw)
data_fsm = FSM(reset_state="IDLE") self.submodules.data_fsm = data_fsm = FSM(reset_state="IDLE")
self.submodules += data_fsm
self.error = error = Signal() self.data_error = Signal()
self.actual = actual = Signal(dram_port.aw) self.comb += self.data_error.eq(dma.source.data != gen.o)
self.expect = expect = Signal(dram_port.aw)
self.comb += [
actual.eq(dma.source.data),
expect.eq(gen.o),
error.eq(dma.source.valid & (expect != actual)),
]
data_fsm.act("IDLE", data_fsm.act("IDLE",
If(self.start, If(self.start,
@ -245,7 +235,7 @@ class _LiteDRAMBISTChecker(Module, AutoCSR):
If(dma.source.valid, If(dma.source.valid,
gen.ce.eq(1), gen.ce.eq(1),
NextValue(data_counter, data_counter + 1), NextValue(data_counter, data_counter + 1),
If(error, If(self.data_error,
NextValue(self.err_count, self.err_count + 1), NextValue(self.err_count, self.err_count + 1),
), ),
If(data_counter == (self.length-1), If(data_counter == (self.length-1),
@ -255,8 +245,8 @@ class _LiteDRAMBISTChecker(Module, AutoCSR):
) )
data_fsm.act("DONE") data_fsm.act("DONE")
self.comb += self.done.eq( self.comb += self.done.eq(cmd_fsm.ongoing("DONE") &
cmd_fsm.ongoing("DONE") & data_fsm.ongoing("DONE")) data_fsm.ongoing("DONE"))
class LiteDRAMBISTChecker(Module, AutoCSR): class LiteDRAMBISTChecker(Module, AutoCSR):
@ -298,8 +288,7 @@ class LiteDRAMBISTChecker(Module, AutoCSR):
core = ResetInserter()(_LiteDRAMBISTChecker(dram_port, random)) core = ResetInserter()(_LiteDRAMBISTChecker(dram_port, random))
self.submodules.core = ClockDomainsRenamer(cd)(core) self.submodules.core = ClockDomainsRenamer(cd)(core)
#reset_sync = PulseSynchronizer("sys", cd) reset_sync = PulseSynchronizer("sys", cd)
reset_sync = BusSynchronizer(1, "sys", cd)
start_sync = PulseSynchronizer("sys", cd) start_sync = PulseSynchronizer("sys", cd)
self.submodules += reset_sync, start_sync self.submodules += reset_sync, start_sync
self.comb += [ self.comb += [