frontend/avalon: Remove cmd_fifo (not useful).
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@ -55,7 +55,6 @@ class LiteDRAMAvalonMM2Native(LiteXModule):
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self.comb += address_offset.eq(base_address >> log2_int(port.data_width//8))
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# Layouts.
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cmd_layout = [("address", len(address))]
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wdata_layout = [
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("data", avalon_data_width),
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("byteenable", avalon_data_width//8),
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@ -136,34 +135,26 @@ class LiteDRAMAvalonMM2Native(LiteXModule):
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wdata_fifo.source.ready.eq(port.wdata.ready),
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]
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self.cmd_fifo = cmd_fifo = stream.SyncFIFO(cmd_layout, max_burst_length)
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fsm.act("BURST_WRITE",
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# FIFO producer
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avalon.waitrequest.eq(~(cmd_fifo.sink.ready & wdata_fifo.sink.ready)),
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cmd_fifo.sink.payload.address.eq(address),
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cmd_fifo.sink.valid.eq(avalon.write & ~avalon.waitrequest),
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If(avalon.write & (burst_count > 0),
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If(cmd_fifo.sink.ready & cmd_fifo.sink.valid,
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avalon.waitrequest.eq(1),
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port.cmd.addr.eq(address),
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port.cmd.we.eq(1),
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port.cmd.valid.eq(avalon.write & wdata_fifo.sink.ready),
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If(port.cmd.valid & port.cmd.ready,
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avalon.waitrequest.eq(0)
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),
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If(burst_count > 0,
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If(port.cmd.valid & port.cmd.ready,
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NextValue(burst_count, burst_count - 1),
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NextValue(address, address + burst_increment)
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)
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).Else(
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avalon.waitrequest.eq(1),
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# Wait for the FIFO to be empty
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If((cmd_fifo.level == 0) & (wdata_fifo.level == 1) & port.wdata.ready,
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If((~port.cmd.valid) & (~wdata_fifo.source.valid),
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NextState("START")
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)
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),
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# FIFO consumer
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port.cmd.addr.eq(cmd_fifo.source.payload.address),
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port.cmd.we.eq(port.cmd.valid),
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port.cmd.valid.eq(cmd_fifo.source.valid & (0 < wdata_fifo.level)),
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cmd_fifo.source.ready.eq(port.cmd.ready),
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)
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fsm.act("BURST_READ",
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