Merge pull request #197 from ozbenh/standalone-sim
Allow generation of a standalone sim model
This commit is contained in:
enjoy-digital
GitHub
commit
a8e281f7c5
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@ -37,6 +37,10 @@ from litex.build.xilinx import XilinxPlatform
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from litex.build.lattice import LatticePlatform
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from litex.boards.platforms import versa_ecp5
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from litex.build.sim import SimPlatform
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from litex.tools.litex_sim import get_sdram_phy_settings
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from litedram.phy.model import SDRAMPHYModel
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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@ -296,7 +300,7 @@ class LiteDRAMCoreControl(Module, AutoCSR):
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# LiteDRAMCore -------------------------------------------------------------------------------------
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class LiteDRAMCore(SoCCore):
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def __init__(self, platform, core_config, **kwargs):
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def __init__(self, platform, core_config, is_sim=False, **kwargs):
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platform.add_extension(get_common_ios())
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# Parameters -------------------------------------------------------------------------------
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@ -304,6 +308,9 @@ class LiteDRAMCore(SoCCore):
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cpu_type = core_config["cpu"]
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cpu_variant = core_config.get("cpu_variant", "standard")
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csr_alignment = core_config.get("csr_alignment", 32)
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csr_data_width= core_config.get("csr_data_width", None)
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if csr_data_width is not None:
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kwargs["csr_data_width"] = csr_data_width
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if cpu_type is None:
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kwargs["integrated_rom_size"] = 0
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kwargs["integrated_sram_size"] = 0
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@ -313,21 +320,38 @@ class LiteDRAMCore(SoCCore):
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq,
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cpu_type = cpu_type,
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cpu_variant = cpu_variant,
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csr_alignment = csr_alignment,
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cpu_type = cpu_type,
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cpu_variant = cpu_variant,
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csr_alignment = csr_alignment,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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if core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]:
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if is_sim:
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self.submodules.crg = CRG(platform.request("clk"))
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elif core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]:
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self.submodules.crg = crg = LiteDRAMECP5DDRPHYCRG(platform, core_config)
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if core_config["sdram_phy"] in [litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY, litedram_phys.V7DDRPHY]:
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elif core_config["sdram_phy"] in [litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY, litedram_phys.V7DDRPHY]:
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self.submodules.crg = LiteDRAMS7DDRPHYCRG(platform, core_config)
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# DRAM -------------------------------------------------------------------------------------
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platform.add_extension(get_dram_ios(core_config))
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# ECP5DDRPHY
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if core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]:
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sdram_module = core_config["sdram_module"](sys_clk_freq,
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"1:4" if core_config["memtype"] == "DDR3" else "1:2")
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# Sim
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if is_sim:
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sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings
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phy_settings = get_sdram_phy_settings(
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memtype = sdram_module.memtype,
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data_width = 16, #sdram_data_width, # XXXX FIXME
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clk_freq = sdram_clk_freq)
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self.submodules.ddrphy = SDRAMPHYModel(
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module = sdram_module,
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settings = phy_settings,
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clk_freq = sdram_clk_freq,
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verbosity = 1,
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init = [])
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# ECP5DDRPHY
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elif core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]:
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assert core_config["memtype"] in ["DDR3"]
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self.submodules.ddrphy = core_config["sdram_phy"](
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pads = platform.request("ddram"),
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@ -336,7 +360,7 @@ class LiteDRAMCore(SoCCore):
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self.add_constant("ECP5DDRPHY")
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sdram_module = core_config["sdram_module"](sys_clk_freq, "1:2")
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# S7DDRPHY
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if core_config["sdram_phy"] in [litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY, litedram_phys.V7DDRPHY]:
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elif core_config["sdram_phy"] in [litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY, litedram_phys.V7DDRPHY]:
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assert core_config["memtype"] in ["DDR2", "DDR3"]
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self.submodules.ddrphy = core_config["sdram_phy"](
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pads = platform.request("ddram"),
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@ -353,8 +377,6 @@ class LiteDRAMCore(SoCCore):
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ron = core_config["ron"])
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self.add_csr("ddrphy")
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sdram_module = core_config["sdram_module"](sys_clk_freq,
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"1:4" if core_config["memtype"] == "DDR3" else "1:2")
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controller_settings = controller_settings = ControllerSettings(
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cmd_buffer_depth=core_config["cmd_buffer_depth"])
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self.add_sdram("sdram",
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@ -525,8 +547,10 @@ def main():
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builder_args(parser)
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parser.set_defaults(output_dir="build")
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parser.add_argument("config", help="YAML config file")
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parser.add_argument("--sim", action='store_true', help="Generate a sim model")
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args = parser.parse_args()
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core_config = yaml.load(open(args.config).read(), Loader=yaml.Loader)
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is_sim = args.sim
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# Convert YAML elements to Python/LiteX --------------------------------------------------------
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for k, v in core_config.items():
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@ -542,7 +566,9 @@ def main():
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core_config[k] = getattr(litedram_phys, core_config[k])
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# Generate core --------------------------------------------------------------------------------
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if core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]:
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if is_sim:
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platform = SimPlatform("", io=[])
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elif core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]:
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platform = LatticePlatform("LFE5UM5G-45F-8BG381C", io=[], toolchain="trellis") # FIXME: allow other devices.
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elif core_config["sdram_phy"] in [litedram_phys.A7DDRPHY, litedram_phys.K7DDRPHY, litedram_phys.V7DDRPHY]:
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platform = XilinxPlatform("", io=[], toolchain="vivado")
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@ -552,7 +578,7 @@ def main():
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builder_arguments = builder_argdict(args)
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builder_arguments["compile_gateware"] = False
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soc = LiteDRAMCore(platform, core_config, integrated_rom_size=0x6000)
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soc = LiteDRAMCore(platform, core_config, is_sim=is_sim, integrated_rom_size=0x6000)
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builder = Builder(soc, **builder_arguments)
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vns = builder.build(build_name="litedram_core", regular_comb=False)
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@ -492,7 +492,7 @@ class SDRAMPHYModel(Module):
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self.submodules += timing_checker
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# Bank init data ---------------------------------------------------------------------------
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bank_init = [[] for i in range(nbanks)]
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bank_init = [None for i in range(nbanks)]
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if init:
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bank_init = self.__prepare_bank_init_data(
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