phy/ecp5ddrphy: cosmetic cleanups.
This commit is contained in:
Florent Kermarrec
parent
8c339b9945
commit
a8fa38e286
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@ -40,8 +40,8 @@ class ECP5DDRPHYInit(Module):
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_lock = Signal()
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delay = Signal()
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self.specials += Instance("DDRDLLA",
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i_CLK = ClockSignal("sys2x"),
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i_RST = ResetSignal("init"),
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i_CLK = ClockSignal("sys2x"),
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i_UDDCNTLN = ~update,
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i_FREEZE = freeze,
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o_DDRDEL = delay,
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@ -151,8 +151,8 @@ class ECP5DDRPHY(Module, AutoCSR):
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sd_clk_se = Signal()
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self.specials += Instance("ODDRX2F",
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i_RST = ResetSignal("sys"),
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i_SCLK = ClockSignal("sys"),
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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i_D0 = 0,
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i_D1 = 1,
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i_D2 = 0,
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@ -164,8 +164,8 @@ class ECP5DDRPHY(Module, AutoCSR):
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for i in range(addressbits):
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self.specials += Instance("ODDRX2F",
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i_RST = ResetSignal("sys"),
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i_SCLK = ClockSignal("sys"),
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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i_D0 = dfi.phases[0].address[i],
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i_D1 = dfi.phases[0].address[i],
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i_D2 = dfi.phases[1].address[i],
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@ -175,8 +175,8 @@ class ECP5DDRPHY(Module, AutoCSR):
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for i in range(bankbits):
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self.specials += Instance("ODDRX2F",
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i_RST = ResetSignal("sys"),
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i_SCLK = ClockSignal("sys"),
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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i_D0 = dfi.phases[0].bank[i],
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i_D1 = dfi.phases[0].bank[i],
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i_D2 = dfi.phases[1].bank[i],
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@ -192,8 +192,8 @@ class ECP5DDRPHY(Module, AutoCSR):
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for i in range(len(getattr(pads, name))):
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self.specials += Instance("ODDRX2F",
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i_RST = ResetSignal("sys"),
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i_SCLK = ClockSignal("sys"),
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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i_D0 = getattr(dfi.phases[0], name)[i],
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i_D1 = getattr(dfi.phases[0], name)[i],
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i_D2 = getattr(dfi.phases[1], name)[i],
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@ -203,7 +203,7 @@ class ECP5DDRPHY(Module, AutoCSR):
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# DQ ---------------------------------------------------------------------------------------
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dq_oe = Signal()
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dqs_re = Signal()
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dqs_re = Signal()
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dqs_oe = Signal()
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dqs_postamble = Signal()
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dqs_preamble = Signal()
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@ -216,25 +216,20 @@ class ECP5DDRPHY(Module, AutoCSR):
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rdpntr = Signal(3)
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wrpntr = Signal(3)
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rdly = Signal(7)
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self.sync += \
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If(self._dly_sel.storage[i],
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If(self._rdly_dq_rst.re,
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rdly.eq(0),
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).Elif(self._rdly_dq_inc.re,
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rdly.eq(rdly + 1),
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)
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)
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datavalid = Signal()
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burstdet = Signal()
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burstdet = Signal()
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self.sync += [
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If(self._dly_sel.storage[i] & self._rdly_dq_rst.re, rdly.eq(0)),
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If(self._dly_sel.storage[i] & self._rdly_dq_inc.re, rdly.eq(rdly + 1))
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]
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self.specials += Instance("DQSBUFM",
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p_DQS_LI_DEL_ADJ = "MINUS",
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p_DQS_LI_DEL_VAL = 1,
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p_DQS_LO_DEL_ADJ = "MINUS",
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p_DQS_LO_DEL_VAL = 4,
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# Clocks / Reset
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i_RST = ResetSignal("sys"),
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i_SCLK = ClockSignal("sys"),
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i_ECLK = ClockSignal("sys2x"),
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i_RST = ResetSignal("sys"),
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i_DDRDEL = self.init.delay,
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i_PAUSE = self.init.pause | self._dly_sel.storage[i],
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@ -276,9 +271,9 @@ class ECP5DDRPHY(Module, AutoCSR):
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]
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# DQS and DM ---------------------------------------------------------------------------
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dm_o_data = Signal(8)
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dm_o_data_d = Signal(8)
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dm_o_data_muxed = Signal(4)
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dm_o_data = Signal(8)
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dm_o_data_d = Signal(8)
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dm_o_data_muxed = Signal(4)
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self.comb += dm_o_data.eq(Cat(
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dfi.phases[0].wrdata_mask[0*databits//8+i],
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dfi.phases[0].wrdata_mask[1*databits//8+i],
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@ -297,8 +292,8 @@ class ECP5DDRPHY(Module, AutoCSR):
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self.sync += Case(bl8_chunk, dm_bl8_cases)
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self.specials += Instance("ODDRX2DQA",
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i_RST = ResetSignal("sys"),
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i_SCLK = ClockSignal("sys"),
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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i_DQSW270 = dqsw270,
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i_D0 = dm_o_data_muxed[0],
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i_D1 = dm_o_data_muxed[1],
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@ -312,8 +307,8 @@ class ECP5DDRPHY(Module, AutoCSR):
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self.specials += [
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Instance("ODDRX2DQSB",
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i_RST = ResetSignal("sys"),
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i_SCLK = ClockSignal("sys"),
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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i_DQSW = dqsw,
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i_D0 = 0,
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i_D1 = 1,
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@ -323,8 +318,8 @@ class ECP5DDRPHY(Module, AutoCSR):
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),
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Instance("TSHX2DQSA",
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i_RST = ResetSignal("sys"),
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i_SCLK = ClockSignal("sys"),
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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i_DQSW = dqsw,
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i_T0 = ~(dqs_oe | dqs_postamble),
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i_T1 = ~(dqs_oe | dqs_preamble),
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@ -361,8 +356,8 @@ class ECP5DDRPHY(Module, AutoCSR):
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self.specials += [
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Instance("ODDRX2DQA",
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i_RST = ResetSignal("sys"),
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i_SCLK = ClockSignal("sys"),
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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i_DQSW270 = dqsw270,
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i_D0 = dq_o_data_muxed[0],
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i_D1 = dq_o_data_muxed[1],
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@ -380,8 +375,8 @@ class ECP5DDRPHY(Module, AutoCSR):
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),
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Instance("IDDRX2DQA",
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i_RST = ResetSignal("sys"),
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i_SCLK = ClockSignal("sys"),
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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i_DQSR90 = dqsr90,
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i_RDPNTR0 = rdpntr[0],
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i_RDPNTR1 = rdpntr[1],
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@ -396,6 +391,7 @@ class ECP5DDRPHY(Module, AutoCSR):
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o_Q3 = dq_i_data[3],
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)
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]
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dq_i_bitslip = BitSlip(4,
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rst = self._dly_sel.storage[i] & self._rdly_dq_bitslip_rst.re,
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slp = self._dly_sel.storage[i] & self._rdly_dq_bitslip.re,
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@ -417,8 +413,8 @@ class ECP5DDRPHY(Module, AutoCSR):
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self.specials += [
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Instance("TSHX2DQA",
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i_RST = ResetSignal("sys"),
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i_SCLK = ClockSignal("sys"),
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i_ECLK = ClockSignal("sys2x"),
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i_SCLK = ClockSignal(),
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i_DQSW270 = dqsw270,
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i_T0 = ~dq_oe,
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i_T1 = ~dq_oe,
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