phy/gw2ddrphy: Make oen signal names consistent.
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22b823fdbc
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@ -315,8 +315,8 @@ class GW2DDRPHY(Module, AutoCSR):
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]
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# DQS ----------------------------------------------------------------------------------
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dqs = Signal()
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dqs_oe_pad = Signal()
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dqs_o = Signal()
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dqs_o_oen = Signal()
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self.specials += [
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Instance("OSER4_MEM",
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i_RESET = ResetSignal("sys"),
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@ -326,12 +326,12 @@ class GW2DDRPHY(Module, AutoCSR):
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i_TX0 = ~(dqs_oe | dqs_postamble), # CHECKME: Polarity + Latency.
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i_TX1 = ~(dqs_oe | dqs_preamble), # CHECKME: Polatiry + Latency.
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**{f"i_D{n}": (0b1010 >> n) & 0b1 for n in range(4)},
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o_Q0 = dqs,
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o_Q1 = dqs_oe_pad
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o_Q0 = dqs_o,
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o_Q1 = dqs_o_oen
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),
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Instance("ELVDS_IOBUF",
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i_I = dqs,
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i_OEN = dqs_oe_pad,
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i_I = dqs_o,
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i_OEN = dqs_o_oen,
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o_O = dqs_i,
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io_IO = pads.dqs_p[i],
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io_IOB = pads.dqs_n[i]
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@ -363,7 +363,7 @@ class GW2DDRPHY(Module, AutoCSR):
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# DQ -----------------------------------------------------------------------------------
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for j in range(8*i, 8*(i+1)):
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dq_o = Signal()
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dq_o_q1 = Signal()
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dq_o_oen = Signal()
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dq_i = Signal()
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dq_i_data = Signal(8)
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dq_o_data = Signal(8)
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@ -387,7 +387,7 @@ class GW2DDRPHY(Module, AutoCSR):
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i_TX1 = ~dq_oe, # CHECKME: Polarity + Latency.
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**{f"i_D{n}": dq_o_data_muxed[n] for n in range(4)},
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o_Q0 = dq_o,
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o_Q1 = dq_o_q1,
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o_Q1 = dq_o_oen,
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),
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]
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dq_i_bitslip = BitSlip(4,
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@ -416,7 +416,7 @@ class GW2DDRPHY(Module, AutoCSR):
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self.specials += [
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Instance("IOBUF",
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i_I = dq_o,
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i_OEN = dq_o_q1,
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i_OEN = dq_o_oen,
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o_O = dq_i,
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io_IO = pads.dq[j]
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)
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