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https://github.com/enjoy-digital/litedram.git
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lpddr5: wck sync: fix syncing and adjusted unit tests
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
This commit is contained in:
Alessandro Comodi
parent
c4273146c1
commit
abc77f367c
3 changed files with 93 additions and 21 deletions
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@ -704,8 +704,8 @@ def get_lpddr5_phy_init_sequence(phy_settings, timing_settings):
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mr[18] = reg([
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(0, 3, rzq_map[wck_odt]),
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(3, 1, 0), # WCK low frequency mode
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(4, 1, 0), # WCK always on mode enabled
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(6, 1, 0), # WCK2CK leveling diabled
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(4, 1, 0), # WCK always on mode disabled
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(6, 1, 0), # WCK2CK leveling disabled
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(7, 1, {2: 1, 4: 0}[wck_ck_ratio]),
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])
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# MR19 - defaults
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@ -303,10 +303,12 @@ class LPDDR5PHY(Module, AutoCSR):
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wck_pattern = Signal(8) # for WCK:CK=2:1 we take wck_pattern[::2]
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patterns = {
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"disabled": "________",
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"static": "________",
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"toggle": "--__--__",
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"toggle_4:1": "-_-_-_-_",
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"disabled": "________",
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"static": "________",
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"toggle": "--__--__",
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"toggle_4:1": "-_-_-_-_",
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"postamble": "--______",
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"postamble_4:1": "-_-_-___",
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}
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assert frange.t_wckpre_static > 0 # The algorithm assumes it's never 0
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@ -332,7 +334,7 @@ class LPDDR5PHY(Module, AutoCSR):
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wck_fsm.act("TOGGLE",
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wck_pattern.eq(bitpattern(patterns["toggle"])),
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If(~wck_sync_done,
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NextState("DISABLED")
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NextState("POSTAMBLE")
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).Elif((wck_ck_ratio == 4), # go to full speed in the next cycle
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NextState("TOGGLE_4:1")
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),
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@ -340,9 +342,22 @@ class LPDDR5PHY(Module, AutoCSR):
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wck_fsm.act("TOGGLE_4:1",
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wck_pattern.eq(bitpattern(patterns["toggle_4:1"])),
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If(~wck_sync_done,
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NextState("DISABLED")
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NextState("POSTAMBLE")
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),
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)
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wck_fsm.act("POSTAMBLE",
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If((wck_ck_ratio == 4),
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wck_pattern.eq(bitpattern(patterns["postamble_4:1"])),
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NextState("DISABLED")
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).Else(
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wck_pattern.eq(bitpattern(patterns["toggle"])),
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NextState("POSTAMBLE_2:1")
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)
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)
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wck_fsm.act("POSTAMBLE_2:1",
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wck_pattern.eq(bitpattern(patterns["postamble"])),
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NextState("DISABLED")
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)
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wck_out = {2: wck_pattern[::2], 4: wck_pattern}[wck_ck_ratio]
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assert len(wck_out) == len(self.out.wck[0]), (len(wck_out), len(self.out.wck))
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@ -424,17 +439,22 @@ class LPDDR5PHY(Module, AutoCSR):
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self.dfi.p0.rddata_valid.eq(rddata_converter.source.valid),
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]
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# -2 is to take into account the serialization time for wck
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read_wck_latency = cmd_latency + cl + burst_ck_cycles - 2
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write_wck_latency = cmd_latency + cwl + burst_ck_cycles - 2
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self.wck_sync_state = Signal(2)
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self.sync += If(self.adapter.wck_sync != 0,
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wck_sync_done.eq(1),
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self.wck_sync_state.eq(self.adapter.wck_sync)
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).Elif(self.wck_sync_state == WCKSyncType.RD,
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If(reduce(or_, rddata_en.taps[0:rddata_start+burst_ck_cycles]) == 0,
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If(reduce(or_, rddata_en.taps[0:read_wck_latency]) == 0,
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wck_sync_done.eq(0),
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self.wck_sync_state.eq(0b00),
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)
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).Elif(self.wck_sync_state == WCKSyncType.WR,
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If(reduce(or_, wrdata_en.taps[0:wrtap+burst_ck_cycles]) == 0,
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If(reduce(or_, wrdata_en.taps[0:write_wck_latency]) == 0,
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wck_sync_done.eq(0),
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self.wck_sync_state.eq(0b00),
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)
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@ -185,7 +185,7 @@ class LPDDR5Tests(unittest.TestCase):
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read, # with WCK sync
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{},
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{},
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read, # no WCK sync
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read, # with WCK sync
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{},
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{},
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],
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@ -215,7 +215,7 @@ class LPDDR5Tests(unittest.TestCase):
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mrr, # with WCK sync
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{},
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{},
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mrr, # no WCK sync
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mrr, # with WCK sync
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{},
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{},
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],
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@ -249,7 +249,7 @@ class LPDDR5Tests(unittest.TestCase):
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write, # with WCK sync
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{},
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{},
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write, # no WCK sync
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write, # with WCK sync
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{},
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{},
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],
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@ -291,12 +291,12 @@ class LPDDR5Tests(unittest.TestCase):
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dfi_sequence = [
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{},
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{0: read}, {}, # WCK sync
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{0: write_ap}, {}, # no WCK sync
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{0: write_ap}, {}, # with WCK sync
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{0: activate}, {},
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{0: refresh_ab},{},
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{0: precharge}, {},
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{0: mrw}, {},
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{0: mrr}, {}, # no WCK sync
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{0: mrr}, {}, # with WCK sync
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{0: zqc_start}, {},
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{0: zqc_latch}, {},
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],
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@ -497,12 +497,31 @@ class LPDDR5Tests(unittest.TestCase):
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0: dict(wrdata=0xfffefffffffefffffffefffffffefffffffefffffffefffffffefffffffeffff),
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}
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latency = [{}] * (wl - 1)
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# minimum latency to have correct wck synchronization
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consecutive_burst_latency = [{}] * 6
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wck_preamble = "00 00" * t["t_wckenl_wr"] + "00 00" * t["t_wckenl_static"] + "10 10" * t["t_wckenl_toggle_wr"]
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wck_burst = "10 10" * (16//4)
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wck_postamble = "10 10" + "10 00"
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self.run_test(phy,
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dfi_sequence = [
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{0: dict(cs_n=0, cas_n=0, ras_n=1, we_n=0, wrdata_en=1)},
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*latency,
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dfi_data
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dfi_data,
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*consecutive_burst_latency,
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{0: dict(cs_n=0, cas_n=0, ras_n=1, we_n=0, wrdata_en=1)},
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*latency,
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dfi_data,
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*consecutive_burst_latency,
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{0: dict(cs_n=0, cas_n=0, ras_n=1, we_n=0, wrdata_en=1)},
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*latency,
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dfi_data,
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*consecutive_burst_latency,
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{0: dict(cs_n=0, cas_n=0, ras_n=1, we_n=0, wrdata_en=1)},
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*latency,
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dfi_data,
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],
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pad_checkers = {
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"sys_270": {
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@ -516,7 +535,10 @@ class LPDDR5Tests(unittest.TestCase):
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# tWCKENL_WR starts counting from first command (CAS) so we add command latency,
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# then preamble, then toggle for the whole burst, then postamble for tWCKPST=2.5tCK
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# (but for now we assume that WCK is never disabled)
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"wck0": "0000 0000" + wck_preamble + "10 10" * (16//4) + "10 10 1" + "0 10" + "00 00"*2,
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"wck0": "0000 0000" + wck_preamble + wck_burst + wck_postamble + \
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"0000" + wck_preamble + wck_burst + wck_postamble + \
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"0000" + wck_preamble + wck_burst + wck_postamble + \
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"0000" + wck_preamble + wck_burst + wck_postamble,
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},
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},
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chunk_size=4,
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@ -540,12 +562,31 @@ class LPDDR5Tests(unittest.TestCase):
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0: dict(wrdata=0xfffefffffffefffffffefffffffefffffffefffffffefffffffefffffffeffff),
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}
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latency = [{}] * (wl - 1)
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# minimum latency to have correct wck synchronization
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consecutive_burst_latency = [{}] * 3
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wck_preamble = "00000000" * (t["t_wckenl_wr"] + t["t_wckenl_static"]) + "11001100" + "10101010" * (t["t_wckenl_toggle_wr"] - 1)
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wck_burst = "10101010" * (16//8)
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wck_postamble = "10101000"
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self.run_test(phy,
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dfi_sequence = [
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{0: dict(cs_n=0, cas_n=0, ras_n=1, we_n=0, wrdata_en=1)},
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*latency,
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dfi_data
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dfi_data,
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*consecutive_burst_latency,
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{0: dict(cs_n=0, cas_n=0, ras_n=1, we_n=0, wrdata_en=1)},
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*latency,
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dfi_data,
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*consecutive_burst_latency,
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{0: dict(cs_n=0, cas_n=0, ras_n=1, we_n=0, wrdata_en=1)},
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*latency,
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dfi_data,
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*consecutive_burst_latency,
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{0: dict(cs_n=0, cas_n=0, ras_n=1, we_n=0, wrdata_en=1)},
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*latency,
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dfi_data,
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],
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pad_checkers = {
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"sys_270": {
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@ -559,7 +600,10 @@ class LPDDR5Tests(unittest.TestCase):
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# tWCKENL_WR starts counting from first command (CAS) so we add command latency,
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# then preamble, then toggle for the whole burst, then postamble for tWCKPST=2.5tCK
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# (but for now we assume that WCK is never disabled)
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"wck0": "00000000 00000000" + wck_preamble + "10101010" * (16//8) + "10101" + "0 10" + "10 10"*2,
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"wck0": "00000000 00000000" + wck_preamble + wck_burst + wck_postamble + \
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"00000000" + wck_preamble + wck_burst + wck_postamble + \
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"00000000" + wck_preamble + wck_burst + wck_postamble + \
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"00000000" + wck_preamble + wck_burst + wck_postamble,
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},
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},
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)
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@ -579,7 +623,11 @@ class LPDDR5Tests(unittest.TestCase):
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phy = LPDDR5SimPHY(sys_clk_freq=sys_clk_freq)
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rl = phy.settings.read_latency
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latency = [{}] * (rl - 1)
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wck_preamble = "00 00" * t["t_wckenl_rd"] + "00 00" * t["t_wckenl_static"] + "10 10" * t["t_wckenl_toggle_rd"]
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wck_burst = "10 10" * (16//4)
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wck_postamble = "10 10" + "10 00"
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self.run_test(phy,
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dfi_sequence = [
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{0: dict(cs_n=0, cas_n=0, ras_n=1, we_n=1, rddata_en=1)},
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@ -591,7 +639,7 @@ class LPDDR5Tests(unittest.TestCase):
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"cs": "01100000",
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},
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"sys4x_270": {
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"wck0": "0000 0000" + wck_preamble + "10 10" * (16//4) + "10 10 1" + "0 10" + "10 10"*2,
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"wck0": "0000 0000" + wck_preamble + wck_burst + wck_postamble + "00 00",
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},
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},
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chunk_size=4,
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@ -612,7 +660,11 @@ class LPDDR5Tests(unittest.TestCase):
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phy = LPDDR5SimPHY(sys_clk_freq=sys_clk_freq, wck_ck_ratio=4)
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rl = phy.settings.read_latency
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latency = [{}] * (rl - 1)
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wck_preamble = "00000000" * (t["t_wckenl_rd"] + t["t_wckenl_static"]) + "11001100" + "10101010" * (t["t_wckenl_toggle_rd"] - 1)
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wck_burst = "10101010" * (16//8)
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wck_postamble = "10101000"
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self.run_test(phy,
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dfi_sequence = [
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{0: dict(cs_n=0, cas_n=0, ras_n=1, we_n=1, rddata_en=1)},
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@ -624,7 +676,7 @@ class LPDDR5Tests(unittest.TestCase):
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"cs": "01100000",
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},
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"sys8x_270": {
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"wck0": "00000000 00000000" + wck_preamble + "10101010" * (16//8) + "10101" + "0 10" + "10 10"*2,
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"wck0": "00000000 00000000" + wck_preamble + wck_burst + wck_postamble + "00000000",
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},
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},
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)
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