Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

test: add random address generation to BIST

This commit is contained in:
Jędrzej Boczar 2020-02-11 12:54:01 +01:00
parent 6744cf649c
commit abf6d1c3d6
1 changed files with 46 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

41
litedram/frontend/bist.py
View File

@ -136,17 +136,24 @@ class _LiteDRAMBISTGenerator(Module):
self.run = Signal() self.run = Signal()
self.ready = Signal() self.ready = Signal()
self.base = Signal(awidth) self.base = Signal(awidth)
self.end = Signal(awidth)
self.length = Signal(awidth) self.length = Signal(awidth)
self.random = Signal() self.random_data = Signal()
self.random_addr = Signal()
self.ticks = Signal(32) self.ticks = Signal(32)
# # # # # #
# Data / Address generators ---------------------------------------------------------------- # Data / Address generators ----------------------------------------------------------------
data_gen = Generator(31, n_state=31, taps=[27, 30]) # PRBS31 data_gen = Generator(31, n_state=31, taps=[27, 30]) # PRBS31
addr_gen = CEInserter()(Counter(awidth)) addr_gen = Generator(31, n_state=31, taps=[27, 30])
self.submodules += data_gen, addr_gen self.submodules += data_gen, addr_gen
self.comb += data_gen.random_enable.eq(self.random) self.comb += data_gen.random_enable.eq(self.random_data)
self.comb += addr_gen.random_enable.eq(self.random_addr)
# mask random address to the range <base, end), range size must be power of 2
addr_mask = Signal(awidth)
self.comb += addr_mask.eq((self.end - self.base) - 1)
# DMA -------------------------------------------------------------------------------------- # DMA --------------------------------------------------------------------------------------
dma = LiteDRAMDMAWriter(dram_port) dma = LiteDRAMDMAWriter(dram_port)
@ -189,14 +196,18 @@ class _LiteDRAMBISTGenerator(Module):
self.ready.eq(1), self.ready.eq(1),
self.done.eq(1) self.done.eq(1)
) )
if isinstance(dram_port, LiteDRAMNativePort): # addressing in dwords if isinstance(dram_port, LiteDRAMNativePort): # addressing in dwords
self.comb += dma.sink.address.eq(self.base[ashift:] + addr_gen.o) dma_sink_addr = dma.sink.address
elif isinstance(dram_port, LiteDRAMAXIPort): # addressing in bytes elif isinstance(dram_port, LiteDRAMAXIPort): # addressing in bytes
self.comb += dma.sink.address[ashift:].eq(self.base[ashift:] + addr_gen.o) dma_sink_addr = dma.sink.address[ashift:]
else: else:
raise NotImplementedError raise NotImplementedError
self.comb += dma_sink_addr.eq(self.base[ashift:] + (addr_gen.o & addr_mask))
self.comb += dma.sink.data.eq(data_gen.o) self.comb += dma.sink.data.eq(data_gen.o)
@ResetInserter() @ResetInserter()
class _LiteDRAMPatternGenerator(Module): class _LiteDRAMPatternGenerator(Module):
def __init__(self, dram_port, init=[]): def __init__(self, dram_port, init=[]):
@ -377,8 +388,10 @@ class _LiteDRAMBISTChecker(Module, AutoCSR):
self.run = Signal() self.run = Signal()
self.ready = Signal() self.ready = Signal()
self.base = Signal(awidth) self.base = Signal(awidth)
self.end = Signal(awidth)
self.length = Signal(awidth) self.length = Signal(awidth)
self.random = Signal() self.random_data = Signal()
self.random_addr = Signal()
self.ticks = Signal(32) self.ticks = Signal(32)
self.errors = Signal(32) self.errors = Signal(32)
@ -386,9 +399,14 @@ class _LiteDRAMBISTChecker(Module, AutoCSR):
# Data / Address generators ---------------------------------------------------------------- # Data / Address generators ----------------------------------------------------------------
data_gen = Generator(31, n_state=31, taps=[27, 30]) # PRBS31 data_gen = Generator(31, n_state=31, taps=[27, 30]) # PRBS31
addr_gen = CEInserter()(Counter(awidth)) addr_gen = Generator(31, n_state=31, taps=[27, 30])
self.submodules += data_gen, addr_gen self.submodules += data_gen, addr_gen
self.comb += data_gen.random_enable.eq(self.random) self.comb += data_gen.random_enable.eq(self.random_data)
self.comb += addr_gen.random_enable.eq(self.random_addr)
# mask random address to the range <base, end), range size must be power of 2
addr_mask = Signal(awidth)
self.comb += addr_mask.eq((self.end - self.base) - 1)
# DMA -------------------------------------------------------------------------------------- # DMA --------------------------------------------------------------------------------------
dma = LiteDRAMDMAReader(dram_port) dma = LiteDRAMDMAReader(dram_port)
@ -428,13 +446,16 @@ class _LiteDRAMBISTChecker(Module, AutoCSR):
) )
) )
cmd_fsm.act("DONE") cmd_fsm.act("DONE")
if isinstance(dram_port, LiteDRAMNativePort): # addressing in dwords if isinstance(dram_port, LiteDRAMNativePort): # addressing in dwords
self.comb += dma.sink.address.eq(self.base[ashift:] + addr_gen.o) dma_sink_addr = dma.sink.address
elif isinstance(dram_port, LiteDRAMAXIPort): # addressing in bytes elif isinstance(dram_port, LiteDRAMAXIPort): # addressing in bytes
self.comb += dma.sink.address[ashift:].eq(self.base[ashift:] + addr_gen.o) dma_sink_addr = dma.sink.address[ashift:]
else: else:
raise NotImplementedError raise NotImplementedError
self.comb += dma_sink_addr.eq(self.base[ashift:] + (addr_gen.o & addr_mask))
# Data FSM --------------------------------------------------------------------------------- # Data FSM ---------------------------------------------------------------------------------
data_counter = Signal(dram_port.address_width, reset_less=True) data_counter = Signal(dram_port.address_width, reset_less=True)