test: add random address generation to BIST

litedram/frontend/bist.py

@@ -136,17 +136,24 @@ class _LiteDRAMBISTGenerator(Module):
         self.run         = Signal()
         self.ready       = Signal()
         self.base        = Signal(awidth)
+        self.end         = Signal(awidth)
         self.length      = Signal(awidth)
-        self.random = Signal()
+        self.random_data = Signal()
+        self.random_addr = Signal()
         self.ticks       = Signal(32)
 
         # # #
 
         # Data / Address generators ----------------------------------------------------------------
         data_gen = Generator(31, n_state=31, taps=[27, 30]) # PRBS31
-        addr_gen = CEInserter()(Counter(awidth))
+        addr_gen = Generator(31, n_state=31, taps=[27, 30])
         self.submodules += data_gen, addr_gen
-        self.comb += data_gen.random_enable.eq(self.random)
+        self.comb += data_gen.random_enable.eq(self.random_data)
+        self.comb += addr_gen.random_enable.eq(self.random_addr)
+
+        # mask random address to the range <base, end), range size must be power of 2
+        addr_mask = Signal(awidth)
+        self.comb += addr_mask.eq((self.end - self.base) - 1)
 
         # DMA --------------------------------------------------------------------------------------
         dma = LiteDRAMDMAWriter(dram_port)
@@ -189,14 +196,18 @@ class _LiteDRAMBISTGenerator(Module):
             self.ready.eq(1),
             self.done.eq(1)
         )
+
         if isinstance(dram_port, LiteDRAMNativePort): # addressing in dwords
-            self.comb += dma.sink.address.eq(self.base[ashift:] + addr_gen.o)
+            dma_sink_addr = dma.sink.address
         elif isinstance(dram_port, LiteDRAMAXIPort):  # addressing in bytes
-            self.comb += dma.sink.address[ashift:].eq(self.base[ashift:] + addr_gen.o)
+            dma_sink_addr = dma.sink.address[ashift:]
         else:
             raise NotImplementedError
+
+        self.comb += dma_sink_addr.eq(self.base[ashift:] + (addr_gen.o & addr_mask))
         self.comb += dma.sink.data.eq(data_gen.o)
 
+
 @ResetInserter()
 class _LiteDRAMPatternGenerator(Module):
     def __init__(self, dram_port, init=[]):
@@ -377,8 +388,10 @@ class _LiteDRAMBISTChecker(Module, AutoCSR):
         self.run         = Signal()
         self.ready       = Signal()
         self.base        = Signal(awidth)
+        self.end         = Signal(awidth)
         self.length      = Signal(awidth)
-        self.random = Signal()
+        self.random_data = Signal()
+        self.random_addr = Signal()
         self.ticks       = Signal(32)
         self.errors      = Signal(32)
 
@@ -386,9 +399,14 @@ class _LiteDRAMBISTChecker(Module, AutoCSR):
 
         # Data / Address generators ----------------------------------------------------------------
         data_gen = Generator(31, n_state=31, taps=[27, 30]) # PRBS31
-        addr_gen = CEInserter()(Counter(awidth))
+        addr_gen = Generator(31, n_state=31, taps=[27, 30])
         self.submodules += data_gen, addr_gen
-        self.comb += data_gen.random_enable.eq(self.random)
+        self.comb += data_gen.random_enable.eq(self.random_data)
+        self.comb += addr_gen.random_enable.eq(self.random_addr)
+
+        # mask random address to the range <base, end), range size must be power of 2
+        addr_mask = Signal(awidth)
+        self.comb += addr_mask.eq((self.end - self.base) - 1)
 
         # DMA --------------------------------------------------------------------------------------
         dma = LiteDRAMDMAReader(dram_port)
@@ -428,13 +446,16 @@ class _LiteDRAMBISTChecker(Module, AutoCSR):
             )
         )
         cmd_fsm.act("DONE")
+
         if isinstance(dram_port, LiteDRAMNativePort): # addressing in dwords
-            self.comb += dma.sink.address.eq(self.base[ashift:] + addr_gen.o)
+            dma_sink_addr = dma.sink.address
         elif isinstance(dram_port, LiteDRAMAXIPort):  # addressing in bytes
-            self.comb += dma.sink.address[ashift:].eq(self.base[ashift:] + addr_gen.o)
+            dma_sink_addr = dma.sink.address[ashift:]
         else:
             raise NotImplementedError
 
+        self.comb += dma_sink_addr.eq(self.base[ashift:] + (addr_gen.o & addr_mask))
+
         # Data FSM ---------------------------------------------------------------------------------
         data_counter = Signal(dram_port.address_width, reset_less=True)