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phy/x7ddrphy: ease understanding of read latency loop range

This commit is contained in:
Florent Kermarrec 2017-02-10 12:57:08 +01:00
parent 478b8c1df3
commit ac43e0118e
2 changed files with 2 additions and 2 deletions
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2
litedram/phy/a7ddrphy.py
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@ -221,7 +221,7 @@ class A7DDRPHY(Module, AutoCSR):
# 2 cycles CAS # 2 cycles CAS
# 2 cycles through ISERDESE2 # 2 cycles through ISERDESE2
rddata_en = self.dfi.phases[self.settings.rdphase].rddata_en rddata_en = self.dfi.phases[self.settings.rdphase].rddata_en
for i in range(5): for i in range(6-1):
n_rddata_en = Signal() n_rddata_en = Signal()
self.sync += n_rddata_en.eq(rddata_en) self.sync += n_rddata_en.eq(rddata_en)
rddata_en = n_rddata_en rddata_en = n_rddata_en

2
litedram/phy/k7ddrphy.py
View File

@ -274,7 +274,7 @@ class K7DDRPHY(Module, AutoCSR):
# 2 cycles CAS # 2 cycles CAS
# 2 cycles through ISERDESE2 # 2 cycles through ISERDESE2
rddata_en = self.dfi.phases[self.settings.rdphase].rddata_en rddata_en = self.dfi.phases[self.settings.rdphase].rddata_en
for i in range(5): for i in range(6-1):
n_rddata_en = Signal() n_rddata_en = Signal()
self.sync += n_rddata_en.eq(rddata_en) self.sync += n_rddata_en.eq(rddata_en)
rddata_en = n_rddata_en rddata_en = n_rddata_en