modules: improve timings definition (keep retro-compatibility with previous definitions)
This commit is contained in:
Florent Kermarrec
parent
5b02791580
commit
ad0a1d4215
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@ -1,10 +1,17 @@
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from math import ceil
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from collections import namedtuple
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from migen import *
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from litedram.common import GeomSettings, TimingSettings
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_technology_timings = ["tREFI", "tWTR", "tCCD", "tRRD"]
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_TechnologyTimings = namedtuple("TechnologyTimings", _technology_timings)
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_speedgrade_timings = ["tRP", "tRCD", "tWR", "tRFC", "tFAW", "tRC", "tRAS"]
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_SpeedgradeTimings = namedtuple("SpeedgradeTimings", _speedgrade_timings)
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class SDRAMModule:
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"""SDRAM module geometry and timings.
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@ -40,12 +47,25 @@ class SDRAMModule:
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)
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def get(self, name):
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if self.speedgrade is not None and name in ["tRP", "tRCD", "tWR", "tRFC", "tFAW"]:
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name += "_" + self.speedgrade
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try:
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return getattr(self, name)
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except:
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return None
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if name in _speedgrade_timings:
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if hasattr(self, "speedgrade_timings"):
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speedgrade = "default" if self.speedgrade is None else self.speedgrade
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return getattr(self.speedgrade_timings[speedgrade], name)
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else:
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name = name + "_" + self.speedgrade if self.speedgrade is not None else name
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try:
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return getattr(self, name)
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except:
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return None
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else:
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if hasattr(self, "technology_timings"):
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return getattr(self.technology_timings, name)
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else:
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try:
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return getattr(self, name)
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except:
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return None
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def ns_to_cycles_trrd(self, t):
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lower_bound = {
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@ -92,15 +112,10 @@ class IS42S16160(SDRAMModule):
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nbanks = 4
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nrows = 8192
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ncols = 512
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# speedgrade invariant timings
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tREFI = 64e6/8192
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tWTR = (2, None)
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tCCD = (1, None)
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# speedgrade related timings
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tRP = 20
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tRCD = 20
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tWR = 20
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tRFC = 70
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# timings
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technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None)
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speedgrade_timings = {"default": _SpeedgradeTimings(tRP=20, tRCD=20, tWR=20, tRFC=70, tFAW=None, tRC=None, tRAS=None)}
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class MT48LC4M16(SDRAMModule):
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memtype = "SDR"
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@ -108,15 +123,9 @@ class MT48LC4M16(SDRAMModule):
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nbanks = 4
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nrows = 4096
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ncols = 256
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# speedgrade invariant timings
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tREFI = 64e6/4096
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tWTR = (2, None)
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tCCD = (1, None)
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# speedgrade related timings
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tRP = 15
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tRCD = 15
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tWR = 14
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tRFC = 66
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# timings
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technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None)
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speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=14, tRFC=66, tFAW=None, tRC=None, tRAS=None)}
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class AS4C16M16(SDRAMModule):
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@ -125,15 +134,9 @@ class AS4C16M16(SDRAMModule):
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nbanks = 4
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nrows = 8192
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ncols = 512
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# speedgrade invariant timings
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tREFI = 64e6/8192
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tWTR = (2, None)
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tCCD = (1, None)
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# speedgrade related timings
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tRP = 18
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tRCD = 18
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tWR = 12
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tRFC = 60
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# timings
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technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None)
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speedgrade_timings = {"default": _SpeedgradeTimings(tRP=18, tRCD=18, tWR=12, tRFC=60, tFAW=None, tRC=None, tRAS=None)}
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# DDR
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@ -143,15 +146,9 @@ class MT46V32M16(SDRAMModule):
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nbanks = 4
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nrows = 8192
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ncols = 1024
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# speedgrade invariant timings
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tREFI = 64e6/8192
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tWTR = (2, None)
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tCCD = (1, None)
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# speedgrade related timings
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tRP = 15
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tRCD = 15
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tWR = 15
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tRFC = 70
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# timings
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technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None)
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speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=70, tFAW=None, tRC=None, tRAS=None)}
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# LPDDR
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@ -161,15 +158,9 @@ class MT46H32M16(SDRAMModule):
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nbanks = 4
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nrows = 8192
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ncols = 1024
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# speedgrade invariant timings
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tREFI = 64e6/8192
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tWTR = (2, None)
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tCCD = (1, None)
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# speedgrade related timings
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tRP = 15
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tRCD = 15
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tWR = 15
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tRFC = 72
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# timings
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technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=None)
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speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=72, tFAW=None, tRC=None, tRAS=None)}
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class MT46H32M32(SDRAMModule):
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@ -178,15 +169,9 @@ class MT46H32M32(SDRAMModule):
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nbanks = 4
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nrows = 8192
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ncols = 1024
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# speedgrade invariant timings
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tREFI = 64e6/8192
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tWTR = (1, None)
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tCCD = (1, None)
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# speedgrade related timings
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tRP = 15
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tRCD = 15
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tWR = 15
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tRFC = 72
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# timings
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technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(1, None), tCCD=(1, None), tRRD=None)
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speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=72, tFAW=None, tRC=None, tRAS=None)}
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# DDR2
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@ -196,15 +181,9 @@ class MT47H128M8(SDRAMModule):
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nbanks = 8
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nrows = 16384
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ncols = 1024
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# speedgrade invariant timings
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tREFI = 64e6/8192
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tWTR = (None, 7.5)
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tCCD = (2, None)
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# speedgrade related timings
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tRP = 15
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tRCD = 15
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tWR = 15
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tRFC = 127.5
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# timings
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technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(None, 7.5), tCCD=(2, None), tRRD=None)
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speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=127.5, tFAW=None, tRC=None, tRAS=None)}
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class MT47H64M16(SDRAMModule):
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@ -213,16 +192,9 @@ class MT47H64M16(SDRAMModule):
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nbanks = 8
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nrows = 8192
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ncols = 1024
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# speedgrade invariant timings
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tREFI = 64e6/8192
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tWTR = (None, 7.5)
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tCCD = (2, None)
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# speedgrade related timings
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tRP = 15
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tRCD = 15
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tWR = 15
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tREFI = 64e6/8192
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tRFC = 127.5
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# timings
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technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(None, 7.5), tCCD=(2, None), tRRD=None)
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speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=127.5, tFAW=None, tRC=None, tRAS=None)}
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class P3R1GE4JGF(SDRAMModule):
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@ -231,16 +203,9 @@ class P3R1GE4JGF(SDRAMModule):
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nbanks = 8
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nrows = 8192
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ncols = 1024
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# speedgrade invariant timings
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tREFI = 64e6/8192
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tWTR = (None, 7.5)
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tCCD = (2, None)
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# speedgrade related timings
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tRP = 12.5
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tRCD = 12.5
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tWR = 15
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tREFI = 64e6/8192
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tRFC = 127.5
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# timings
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technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(None, 7.5), tCCD=(2, None), tRRD=None)
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speedgrade_timings = {"default": _SpeedgradeTimings(tRP=12.5, tRCD=12.5, tWR=15, tRFC=127.5, tFAW=None, tRC=None, tRAS=None)}
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# DDR3 (Chips)
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@ -250,73 +215,43 @@ class MT41J128M16(SDRAMModule):
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nbanks = 8
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nrows = 16384
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ncols = 1024
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# speedgrade invariant timings
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tREFI = 64e6/8192
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tWTR = (4, 7.5)
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tCCD = (4, None)
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tRRD = 10
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# speedgrade related timings
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# DDR3-800
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tRP_800 = 13.1
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tRCD_800 = 13.1
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tWR_800 = 13.1
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tRFC_800 = 64
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tFAW_800 = (None, 50)
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tRC_800 = 50.625
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tRAS_800 = 37.5
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# DDR3-1066
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tRP_1066 = 13.1
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tRCD_1066 = 13.1
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tWR_1066 = 13.1
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tRFC_1066 = 86
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tFAW_1066 = (None, 50)
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tRC_1066 = 50.625
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tRAS_1066 = 37.5
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# DDR3-1333
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tRP_1333 = 13.5
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tRCD_1333 = 13.5
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tWR_1333 = 13.5
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tRFC_1333 = 107
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tFAW_1333 = (None, 45)
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tRC_1333 = 49.5
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tRAS_1333 = 36
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# DDR3-1600
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tRP_1600 = 13.75
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tRCD_1600 = 13.75
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tWR_1600 = 13.75
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tRFC_1600 = 128
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tFAW_1600 = (None, 40)
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tRC_1600 = 48.75
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tRAS_1600 = 35
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# API retro-compatibility
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tRP = tRP_1600
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tRCD = tRCD_1600
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tWR = tWR_1600
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tRFC = tRFC_1600
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tFAW = tFAW_1600
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tRC = tRC_1600
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tRAS = tRAS_1600
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# timings
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technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=10)
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speedgrade_timings = {
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"800": _SpeedgradeTimings(tRP=13.1, tRCD=13.1, tWR=13.1, tRFC=64, tFAW=(None, 50), tRC=50.625, tRAS=37.5),
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"1066": _SpeedgradeTimings(tRP=13.1, tRCD=13.1, tWR=13.1, tRFC=86, tFAW=(None, 50), tRC=50.625, tRAS=37.5),
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"1333": _SpeedgradeTimings(tRP=13.5, tRCD=13.5, tWR=13.5, tRFC=107, tFAW=(None, 45), tRC=49.5, tRAS=36),
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"1600": _SpeedgradeTimings(tRP=13.75, tRCD=13.75, tWR=13.75, tRFC=128, tFAW=(None, 40), tRC=48.75, tRAS=35),
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}
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speedgrade_timings["default"] = speedgrade_timings["1600"]
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class MT41K128M16(MT41J128M16):
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pass
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class MT41J256M16(MT41J128M16):
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class MT41J256M16(SDRAMModule):
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memtype = "DDR3"
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# geometry
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nbanks = 8
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nrows = 32768
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# speedgrade related timings
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tRFC_1066 = 139
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tRFC_1333 = 174
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tRFC_1600 = 208
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# API retro-compatibility
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tRFC = tRFC_1600
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ncols = 1024
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# timings
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technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=10)
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speedgrade_timings = {
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"800": _SpeedgradeTimings(tRP=13.1, tRCD=13.1, tWR=13.1, tRFC=139, tFAW=(None, 50), tRC=50.625, tRAS=37.5),
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"1066": _SpeedgradeTimings(tRP=13.1, tRCD=13.1, tWR=13.1, tRFC=138, tFAW=(None, 50), tRC=50.625, tRAS=37.5),
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"1333": _SpeedgradeTimings(tRP=13.5, tRCD=13.5, tWR=13.5, tRFC=174, tFAW=(None, 45), tRC=49.5, tRAS=36),
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"1600": _SpeedgradeTimings(tRP=13.75, tRCD=13.75, tWR=13.75, tRFC=208, tFAW=(None, 40), tRC=48.75, tRAS=35),
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}
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speedgrade_timings["default"] = speedgrade_timings["1600"]
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class MT41K256M16(MT41J256M16):
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pass
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# FIXME: update to new definition when fully tested (old definition still handled)
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class K4B2G1646FBCK0(SDRAMModule): ### TODO: optimize and revalidate all timings, at cold and hot temperatures
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memtype = "DDR3"
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# geometry
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@ -350,29 +285,13 @@ class MT8JTF12864(SDRAMModule):
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nbanks = 8
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nrows = 16384
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ncols = 1024
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# speedgrade invariant timings
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tREFI = 64e6/8192
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tWTR = (4, 7.5)
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tCCD = (4, None)
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# speedgrade related timings
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# DDR3-1066
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tRP_1066 = 15
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tRCD_1066 = 15
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tWR_1066 = 15
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tRFC_1066 = 86
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tFAW_1066 = (None, 50)
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# DDR3-1333
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tRP_1333 = 15
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tRCD_1333 = 15
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tWR_1333 = 15
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tRFC_1333 = 107
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tFAW_1333 = (None, 45)
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# API retro-compatibility
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tRP = tRP_1333
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tRCD = tRCD_1333
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tWR = tWR_1333
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tRFC = tRFC_1333
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tFAW = tFAW_1333
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# timings
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technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=None)
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speedgrade_timings = {
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"1066": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=86, tFAW=(None, 50), tRC=None, tRAS=None),
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"1333": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=107, tFAW=(None, 45), tRC=None, tRAS=None),
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}
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speedgrade_timings["default"] = speedgrade_timings["1333"]
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class MT18KSF1G72HZ(SDRAMModule):
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@ -381,31 +300,11 @@ class MT18KSF1G72HZ(SDRAMModule):
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nbanks = 8
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nrows = 65536
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ncols = 1024
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# speedgrade invariant timings
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tREFI = 64e6/8192
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tWTR = (4, 7.5)
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tCCD = (4, None)
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# DDR3-1066
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tRP_1066 = 15
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tRCD_1066 = 15
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tWR_1066 = 15
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tRFC_1066 = 86
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tFAW_1066 = (None, 50)
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# DDR3-1333
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tRP_1333 = 15
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tRCD_1333 = 15
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tWR_1333 = 15
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tRFC_1333 = 107
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tFAW_1333 = (None, 45)
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# DDR3-1600
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tRP_1600 = 13.125
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tRCD_1600 = 13.125
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tWR_1600 = 13.125
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tRFC_1600 = 128
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tFAW_1600 = (None, 40)
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# API retro-compatibility
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tRP = tRP_1600
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tRCD = tRCD_1600
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tWR = tWR_1600
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tRFC = tRFC_1600
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tFAW = tFAW_1600
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# timings
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technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(4, 7.5), tCCD=(4, None), tRRD=None)
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speedgrade_timings = {
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"1066": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=86, tFAW=(None, 50), tRC=None, tRAS=None),
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"1333": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=107, tFAW=(None, 45), tRC=None, tRAS=None),
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"1600": _SpeedgradeTimings(tRP=13.125, tRCD=13.125, tWR=13.125, tRFC=128, tFAW=(None, 40), tRC=None, tRAS=None),
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}
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speedgrade_timings["default"] = speedgrade_timings["1600"]
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