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Merge pull request #136 from antmicro/jboc/benchmark 

Benchmark: use Memory instead of Case for custom access pattern
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enjoy-digital 2020-02-08 09:27:27 +01:00 committed by GitHub
parent ab8661405a cf5939f09e
commit ad173d69fb
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1 changed files with 30 additions and 10 deletions
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40
litedram/frontend/bist.py
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@ -195,6 +195,14 @@ class _LiteDRAMPatternGenerator(Module):
# # # # # #
# Data / Address pattern -------------------------------------------------------------------
addr_init, data_init = zip(*init)
addr_mem = Memory(dram_port.address_width, len(addr_init), init=addr_init)
data_mem = Memory(dram_port.data_width, len(data_init), init=data_init)
addr_port = addr_mem.get_port(async_read=True)
data_port = data_mem.get_port(async_read=True)
self.specials += addr_mem, data_mem, addr_port, data_port
# DMA -------------------------------------------------------------------------------------- # DMA --------------------------------------------------------------------------------------
dma = LiteDRAMDMAWriter(dram_port) dma = LiteDRAMDMAWriter(dram_port)
self.submodules += dma self.submodules += dma
@ -232,11 +240,11 @@ class _LiteDRAMPatternGenerator(Module):
else: else:
raise NotImplementedError raise NotImplementedError
addr_cases = {i: dma_sink_addr.eq(addr) for i, (addr, data) in enumerate(init)}
data_cases = {i: dma.sink.data.eq(data) for i, (addr, data) in enumerate(init)}
self.comb += [ self.comb += [
Case(cmd_counter, addr_cases), addr_port.adr.eq(cmd_counter),
Case(cmd_counter, data_cases), dma_sink_addr.eq(addr_port.dat_r),
data_port.adr.eq(cmd_counter),
dma.sink.data.eq(data_port.dat_r),
] ]
# LiteDRAMBISTGenerator ---------------------------------------------------------------------------- # LiteDRAMBISTGenerator ----------------------------------------------------------------------------
@ -432,6 +440,14 @@ class _LiteDRAMPatternChecker(Module, AutoCSR):
# # # # # #
# Data / Address pattern -------------------------------------------------------------------
addr_init, data_init = zip(*init)
addr_mem = Memory(dram_port.address_width, len(addr_init), init=addr_init)
data_mem = Memory(dram_port.data_width, len(data_init), init=data_init)
addr_port = addr_mem.get_port(async_read=True)
data_port = data_mem.get_port(async_read=True)
self.specials += addr_mem, data_mem, addr_port, data_port
# DMA -------------------------------------------------------------------------------------- # DMA --------------------------------------------------------------------------------------
dma = LiteDRAMDMAReader(dram_port) dma = LiteDRAMDMAReader(dram_port)
self.submodules += dma self.submodules += dma
@ -459,21 +475,25 @@ class _LiteDRAMPatternChecker(Module, AutoCSR):
cmd_fsm.act("DONE") cmd_fsm.act("DONE")
if isinstance(dram_port, LiteDRAMNativePort): # addressing in dwords if isinstance(dram_port, LiteDRAMNativePort): # addressing in dwords
dma_addr_sink = dma.sink.address dma_sink_addr = dma.sink.address
elif isinstance(dram_port, LiteDRAMAXIPort): # addressing in bytes elif isinstance(dram_port, LiteDRAMAXIPort): # addressing in bytes
dma_addr_sink = dma.sink.address[ashift:] dma_sink_addr = dma.sink.address[ashift:]
else: else:
raise NotImplementedError raise NotImplementedError
addr_cases = {i: dma_addr_sink.eq(addr) for i, (addr, data) in enumerate(init)} self.comb += [
self.comb += Case(cmd_counter, addr_cases) addr_port.adr.eq(cmd_counter),
dma_sink_addr.eq(addr_port.dat_r),
]
# Data FSM --------------------------------------------------------------------------------- # Data FSM ---------------------------------------------------------------------------------
data_counter = Signal(dram_port.address_width, reset_less=True) data_counter = Signal(dram_port.address_width, reset_less=True)
expected_data = Signal.like(dma.source.data) expected_data = Signal.like(dma.source.data)
data_cases = {i: expected_data.eq(data) for i, (addr, data) in enumerate(init)} self.comb += [
self.comb += Case(data_counter, data_cases) data_port.adr.eq(data_counter),
expected_data.eq(data_port.dat_r),
]
data_fsm = FSM(reset_state="IDLE") data_fsm = FSM(reset_state="IDLE")
self.submodules += data_fsm self.submodules += data_fsm