Merge pull request #267 from antmicro/jboc/lpddr4-update
LPDDR4 minor refactor
This commit is contained in:
enjoy-digital
GitHub
commit
ae139096c0
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@ -59,7 +59,7 @@ class DFIPhaseAdapter(Module):
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----------
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dfi_phase : Record(dfi.phase_description), in
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Input from a single DFI phase.
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masked_write : bool
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masked_write : bool or Signal(1)
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Specifies how DFI write command (cas_n=0, ras_n=1, we_n=0) is interpreted, either
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as LPDDR4 WRITE or MASKED-WRITE. MASKED-WRITE requires larger tCCD, but WRITE does
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not permit masking of data, so if masking is needed MASKED-WRITE has to be used.
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@ -14,29 +14,12 @@ from migen import *
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from litex.soc.interconnect.stream import ClockDomainCrossing
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from litex.soc.interconnect.csr import AutoCSR
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from litedram.common import TappedDelayLine, tXXDController
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from litedram.phy.utils import delayed, edge, SimLogger
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from litedram.common import TappedDelayLine
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from litedram.phy.utils import delayed, edge
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from litedram.phy.sim_utils import SimLogger, PulseTiming, log_level_getter
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from litedram.phy.lpddr4.commands import MPC
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def log_level_getter(log_level):
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"""Parse logging level description
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Log level can be presented in a simple form (e.g. `--log-level=DEBUG`) to specify
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the same level for all modules, or can set different levels for different modules
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e.g. `--log-level=all=INFO,data=DEBUG`.
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"""
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def get_level(name):
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return getattr(SimLogger, name.upper())
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if "=" not in log_level: # simple log_level, e.g. "INFO"
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return lambda _: get_level(log_level)
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# parse log_level in the per-module form, e.g. "--log-level=all=INFO,data=DEBUG"
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per_module = dict(part.split("=") for part in log_level.strip().split(","))
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return lambda module: get_level(per_module.get(module, per_module.get("all", None)))
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class LPDDR4Sim(Module, AutoCSR):
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"""LPDDR4 DRAM simulator
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@ -106,33 +89,6 @@ class LPDDR4Sim(Module, AutoCSR):
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# Commands -----------------------------------------------------------------------------------------
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class PulseTiming(Module):
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"""Timing monitor with pulse input/output
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This module works like `tXXDController` with the following differences:
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* countdown triggered by a low to high pulse on `trigger`
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* `ready` is initially low, only after a trigger it can become high
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* provides `ready_p` which is high only for 1 cycle when `ready` becomes high
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"""
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def __init__(self, t):
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self.trigger = Signal()
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self.ready = Signal()
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self.ready_p = Signal()
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ready_d = Signal()
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triggered = Signal()
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tctrl = tXXDController(t)
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self.submodules += tctrl
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self.sync += If(self.trigger, triggered.eq(1)),
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self.comb += [
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self.ready.eq(triggered & tctrl.ready),
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self.ready_p.eq(edge(self, self.ready)),
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tctrl.valid.eq(edge(self, self.trigger)),
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]
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class CommandsSim(Module, AutoCSR):
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"""Command simulation
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@ -6,7 +6,8 @@
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from migen import *
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from litedram.phy.utils import delayed, Serializer, Deserializer, Latency, SimPad, SimulationPads, SimSerDesMixin
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from litedram.phy.utils import delayed, Serializer, Deserializer, Latency
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from litedram.phy.sim_utils import SimPad, SimulationPads, SimSerDesMixin
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from litedram.phy.lpddr4.basephy import LPDDR4PHY, DoubleRateLPDDR4PHY
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@ -10,7 +10,6 @@ import argparse
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from migen import *
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from litex.build.generic_platform import Pins, Subsignal
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from litex.build.sim import SimPlatform
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from litex.build.sim.config import SimConfig
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from litex.soc.interconnect.csr import CSR
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@ -26,21 +25,12 @@ from litedram.phy.model import DFITimingsChecker, _speedgrade_timings, _technolo
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from litedram.phy.lpddr4.simphy import LPDDR4SimPHY, DoubleRateLPDDR4SimPHY
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from litedram.phy.lpddr4.sim import LPDDR4Sim
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from litedram.phy.sim_utils import Clocks, CRG, Platform
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# Platform -----------------------------------------------------------------------------------------
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_io = [
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# clocks added later
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("sys_rst", 0, Pins(1)),
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("serial", 0,
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Subsignal("source_valid", Pins(1)),
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Subsignal("source_ready", Pins(1)),
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Subsignal("source_data", Pins(8)),
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Subsignal("sink_valid", Pins(1)),
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Subsignal("sink_ready", Pins(1)),
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Subsignal("sink_data", Pins(8)),
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),
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# clocks added in main()
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("lpddr4", 0,
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Subsignal("clk", Pins(1)),
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# Subsignal("clk_n", Pins(1)),
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@ -56,44 +46,8 @@ _io = [
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),
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]
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class Platform(SimPlatform):
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def __init__(self):
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SimPlatform.__init__(self, "SIM", _io)
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# Clocks -------------------------------------------------------------------------------------------
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class Clocks(dict): # FORMAT: {name: {"freq_hz": _, "phase_deg": _}, ...}
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def names(self):
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return list(self.keys())
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def add_io(self, io):
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for name in self.names():
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io.append((name + "_clk", 0, Pins(1)))
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def add_clockers(self, sim_config):
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for name, desc in self.items():
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sim_config.add_clocker(name + "_clk", **desc)
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class _CRG(Module):
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def __init__(self, platform, domains=None):
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if domains is None:
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domains = ["sys"]
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# request() before creating domains to avoid signal renaming problem
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domains = {name: platform.request(name + "_clk") for name in domains}
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self.clock_domains.cd_por = ClockDomain(reset_less=True)
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for name in domains.keys():
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setattr(self.clock_domains, "cd_" + name, ClockDomain(name=name))
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int_rst = Signal(reset=1)
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self.sync.por += int_rst.eq(0)
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self.comb += self.cd_por.clk.eq(self.cd_sys.clk)
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for name, clk in domains.items():
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cd = getattr(self, "cd_" + name)
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self.comb += cd.clk.eq(clk)
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self.comb += cd.rst.eq(int_rst)
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def get_clocks(sys_clk_freq):
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return Clocks({
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"sys": dict(freq_hz=sys_clk_freq),
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@ -115,7 +69,7 @@ class SimSoC(SoCCore):
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def __init__(self, clocks, log_level,
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auto_precharge=False, with_refresh=True, trace_reset=0, disable_delay=False,
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masked_write=True, double_rate_phy=False, finish_after_memtest=False, **kwargs):
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platform = Platform()
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platform = Platform(_io, clocks)
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sys_clk_freq = clocks["sys"]["freq_hz"]
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# SoCCore ----------------------------------------------------------------------------------
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@ -127,7 +81,7 @@ class SimSoC(SoCCore):
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, clocks.names())
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self.submodules.crg = CRG(platform, clocks)
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# Debugging --------------------------------------------------------------------------------
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platform.add_debug(self, reset=trace_reset)
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@ -341,7 +295,6 @@ def main():
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sim_config = SimConfig()
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sys_clk_freq = int(float(args.sys_clk_freq))
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clocks = get_clocks(sys_clk_freq)
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clocks.add_io(_io)
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clocks.add_clockers(sim_config)
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# Configuration --------------------------------------------------------------------------------
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@ -0,0 +1,233 @@
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#
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# This file is part of LiteDRAM.
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#
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# Copyright (c) 2021 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex.build.sim import SimPlatform
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from litex.build.sim.config import SimConfig
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from litex.build.generic_platform import Pins, Subsignal
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from litex.soc.interconnect.csr import CSRStorage, AutoCSR
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from litedram.common import Settings, tXXDController
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from litedram.phy.utils import Serializer, Deserializer, edge
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# PHY ----------------------------------------------------------------------------------------------
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class SimSerDesMixin:
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"""Helper class for easier (de-)serialization to simulation pads."""
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def ser(self, *, i, o, clkdiv, clk, name="", **kwargs):
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assert len(o) == 1
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kwargs = dict(i=i, i_dw=len(i), o=o, o_dw=1, clk=clk, clkdiv=clkdiv,
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name=f"ser_{name}".strip("_"), **kwargs)
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self.submodules += Serializer(**kwargs)
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def des(self, *, i, o, clkdiv, clk, name="", **kwargs):
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assert len(i) == 1
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kwargs = dict(i=i, i_dw=1, o=o, o_dw=len(o), clk=clk, clkdiv=clkdiv,
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name=f"des_{name}".strip("_"), **kwargs)
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self.submodules += Deserializer(**kwargs)
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# Platform -----------------------------------------------------------------------------------------
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class SimPad(Settings):
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def __init__(self, name, width, io=False):
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self.set_attributes(locals())
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class SimulationPads(Module):
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"""Pads for simulation purpose
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Tristate pads are simulated as separate input/output pins (name_i, name_o) and
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an output-enable pin (name_oe). Output pins are to be driven byt the PHY and
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input pins are to be driven by the DRAM simulator. An additional pin without
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a suffix is created and this module will include logic to set this pin to the
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actual value depending on the output-enable signal.
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"""
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def layout(self, **kwargs):
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raise NotImplementedError("Simulation pads layout as a list of SimPad objects")
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def __init__(self, **kwargs):
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for pad in self.layout(**kwargs):
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if pad.io:
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o, i, oe = (f"{pad.name}_{suffix}" for suffix in ["o", "i", "oe"])
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setattr(self, pad.name, Signal(pad.width))
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setattr(self, o, Signal(pad.width, name=o))
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setattr(self, i, Signal(pad.width, name=i))
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setattr(self, oe, Signal(name=oe))
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self.comb += If(getattr(self, oe),
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getattr(self, pad.name).eq(getattr(self, o))
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).Else(
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getattr(self, pad.name).eq(getattr(self, i))
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)
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else:
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setattr(self, pad.name, Signal(pad.width, name=pad.name))
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class Clocks(dict):
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"""Helper for definiting simulation clocks
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Dictionary format is `{name: {"freq_hz": _, "phase_deg": _}, ...}`.
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"""
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def names(self):
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return list(self.keys())
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def add_io(self, io):
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for name in self.names():
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io.append((name + "_clk", 0, Pins(1)))
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def add_clockers(self, sim_config):
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for name, desc in self.items():
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sim_config.add_clocker(name + "_clk", **desc)
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class CRG(Module):
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"""Clock & Reset Generator for Verilator-based simulation"""
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def __init__(self, platform, clock_domains=None):
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if clock_domains is None:
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clock_domains = ["sys"]
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elif isinstance(clock_domains, Clocks):
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clock_domains = list(clock_domains.names())
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# request() before creating clock_domains to avoid signal renaming problem
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clock_domains = {name: platform.request(name + "_clk") for name in clock_domains}
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self.clock_domains.cd_por = ClockDomain(reset_less=True)
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for name in clock_domains.keys():
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setattr(self.clock_domains, "cd_" + name, ClockDomain(name=name))
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int_rst = Signal(reset=1)
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self.sync.por += int_rst.eq(0)
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self.comb += self.cd_por.clk.eq(self.cd_sys.clk)
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for name, clk in clock_domains.items():
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cd = getattr(self, "cd_" + name)
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self.comb += cd.clk.eq(clk)
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self.comb += cd.rst.eq(int_rst)
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class Platform(SimPlatform):
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def __init__(self, io, clocks: Clocks):
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common_io = [
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("sys_rst", 0, Pins(1)),
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("serial", 0,
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Subsignal("source_valid", Pins(1)),
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Subsignal("source_ready", Pins(1)),
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Subsignal("source_data", Pins(8)),
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Subsignal("sink_valid", Pins(1)),
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Subsignal("sink_ready", Pins(1)),
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Subsignal("sink_data", Pins(8)),
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),
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]
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clocks.add_io(common_io)
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SimPlatform.__init__(self, "SIM", common_io + io)
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# Logging ------------------------------------------------------------------------------------------
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class SimLogger(Module, AutoCSR):
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"""Logger for use in simulation
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This module allows for easier message logging when running simulation designs.
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The logger can be used from `comb` context so it the methods can be directly
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used inside `FSM` code. It also provides logging levels that can be used to
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filter messages, either by specifying the default `log_level` or in runtime
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by driving to the `level` signal or using a corresponding CSR.
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"""
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# Allows to use Display inside FSM and to filter log messages by level (statically or dynamically)
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DEBUG = 0
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INFO = 1
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WARN = 2
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ERROR = 3
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NONE = 4
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def __init__(self, log_level=INFO, clk_freq=None):
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self.ops = []
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self.level = Signal(reset=log_level, max=self.NONE)
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self.time_ps = None
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if clk_freq is not None:
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self.time_ps = Signal(64)
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cnt = Signal(64)
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self.sync += cnt.eq(cnt + 1)
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self.comb += self.time_ps.eq(cnt * int(1e12/clk_freq))
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def debug(self, fmt, *args, **kwargs):
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return self.log("[DEBUG] " + fmt, *args, level=self.DEBUG, **kwargs)
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def info(self, fmt, *args, **kwargs):
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return self.log("[INFO] " + fmt, *args, level=self.INFO, **kwargs)
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def warn(self, fmt, *args, **kwargs):
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return self.log("[WARN] " + fmt, *args, level=self.WARN, **kwargs)
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def error(self, fmt, *args, **kwargs):
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return self.log("[ERROR] " + fmt, *args, level=self.ERROR, **kwargs)
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def log(self, fmt, *args, level=DEBUG, once=True):
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cond = Signal()
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if once: # make the condition be triggered only on rising edge
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condition = edge(self, cond)
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else:
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condition = cond
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self.ops.append((level, condition, fmt, args))
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return cond.eq(1)
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def add_csrs(self):
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self._level = CSRStorage(len(self.level), reset=self.level.reset.value)
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self.comb += self.level.eq(self._level.storage)
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def do_finalize(self):
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for level, cond, fmt, args in self.ops:
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if self.time_ps is not None:
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fmt = f"[%16d ps] {fmt}"
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args = (self.time_ps, *args)
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self.sync += If((level >= self.level) & cond, Display(fmt, *args))
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def log_level_getter(log_level):
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"""Parse logging level description
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Log level can be presented in a simple form (e.g. `--log-level=DEBUG`) to specify
|
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the same level for all modules, or can set different levels for different modules
|
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e.g. `--log-level=all=INFO,data=DEBUG`.
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"""
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def get_level(name):
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return getattr(SimLogger, name.upper())
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if "=" not in log_level: # simple log_level, e.g. "INFO"
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return lambda _: get_level(log_level)
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# parse log_level in the per-module form, e.g. "--log-level=all=INFO,data=DEBUG"
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per_module = dict(part.split("=") for part in log_level.strip().split(","))
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return lambda module: get_level(per_module.get(module, per_module.get("all", None)))
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# Simulator ----------------------------------------------------------------------------------------
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class PulseTiming(Module):
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"""Timing monitor with pulse input/output
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This module works like `tXXDController` with the following differences:
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|
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* countdown triggered by a low to high pulse on `trigger`
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* `ready` is initially low, only after a trigger it can become high
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* provides `ready_p` which is high only for 1 cycle when `ready` becomes high
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"""
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def __init__(self, t):
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self.trigger = Signal()
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self.ready = Signal()
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self.ready_p = Signal()
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ready_d = Signal()
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triggered = Signal()
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tctrl = tXXDController(t)
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self.submodules += tctrl
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self.sync += If(self.trigger, triggered.eq(1)),
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self.comb += [
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self.ready.eq(triggered & tctrl.ready),
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self.ready_p.eq(edge(self, self.ready)),
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tctrl.valid.eq(edge(self, self.trigger)),
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]
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@ -14,9 +14,8 @@ from collections import defaultdict
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from migen import *
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from litex.soc.interconnect import stream
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from litex.soc.interconnect.csr import CSRStorage, AutoCSR
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from litedram.common import TappedDelayLine, Settings
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from litedram.common import TappedDelayLine
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def bit(n, val):
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|
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@ -44,6 +43,7 @@ def edge(mod, cond):
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mod.sync += cond_d.eq(cond)
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return ~cond_d & cond
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class ConstBitSlip(Module):
|
||||
def __init__(self, dw, slp, cycles, i=None, o=None, register=True):
|
||||
self.i = Signal(dw, name='i') if i is None else i
|
||||
|
|
@ -73,6 +73,7 @@ class ConstBitSlip(Module):
|
|||
"""Minimum number of cycles to be able to use given bitslip values"""
|
||||
return math.ceil((slp + 1) / dw)
|
||||
|
||||
|
||||
# TODO: rewrite DQSPattern in litedram/common.py to support different data widths
|
||||
class DQSPattern(Module):
|
||||
def __init__(self, preamble=None, postamble=None, wlevel_en=0, wlevel_strobe=0, register=False):
|
||||
|
|
@ -138,39 +139,6 @@ class Latency:
|
|||
return "Latency({} sys clk)".format(self._sys)
|
||||
|
||||
|
||||
class SimPad(Settings):
|
||||
def __init__(self, name, width, io=False):
|
||||
self.set_attributes(locals())
|
||||
|
||||
class SimulationPads(Module):
|
||||
"""Pads for simulation purpose
|
||||
|
||||
Tristate pads are simulated as separate input/output pins (name_i, name_o) and
|
||||
an output-enable pin (name_oe). Output pins are to be driven byt the PHY and
|
||||
input pins are to be driven by the DRAM simulator. An additional pin without
|
||||
a suffix is created and this module will include logic to set this pin to the
|
||||
actual value depending on the output-enable signal.
|
||||
"""
|
||||
def layout(self, **kwargs):
|
||||
raise NotImplementedError("Simulation pads layout as a list of SimPad objects")
|
||||
|
||||
def __init__(self, **kwargs):
|
||||
for pad in self.layout(**kwargs):
|
||||
if pad.io:
|
||||
o, i, oe = (f"{pad.name}_{suffix}" for suffix in ["o", "i", "oe"])
|
||||
setattr(self, pad.name, Signal(pad.width))
|
||||
setattr(self, o, Signal(pad.width, name=o))
|
||||
setattr(self, i, Signal(pad.width, name=i))
|
||||
setattr(self, oe, Signal(name=oe))
|
||||
self.comb += If(getattr(self, oe),
|
||||
getattr(self, pad.name).eq(getattr(self, o))
|
||||
).Else(
|
||||
getattr(self, pad.name).eq(getattr(self, i))
|
||||
)
|
||||
else:
|
||||
setattr(self, pad.name, Signal(pad.width, name=pad.name))
|
||||
|
||||
|
||||
class CommandsPipeline(Module):
|
||||
"""Commands pipeline logic for LPDDR4/LPDDR5
|
||||
|
||||
|
|
@ -339,81 +307,6 @@ class Deserializer(Module):
|
|||
sd_clkdiv += self.o.eq(Cat(as_array(o_pre_d)[:-1], as_array(o_pre)[-1]))
|
||||
|
||||
|
||||
class SimSerDesMixin:
|
||||
"""Helper class for easier (de-)serialization to simulation pads."""
|
||||
def ser(self, *, i, o, clkdiv, clk, name="", **kwargs):
|
||||
assert len(o) == 1
|
||||
kwargs = dict(i=i, i_dw=len(i), o=o, o_dw=1, clk=clk, clkdiv=clkdiv,
|
||||
name=f"ser_{name}".strip("_"), **kwargs)
|
||||
self.submodules += Serializer(**kwargs)
|
||||
|
||||
def des(self, *, i, o, clkdiv, clk, name="", **kwargs):
|
||||
assert len(i) == 1
|
||||
kwargs = dict(i=i, i_dw=1, o=o, o_dw=len(o), clk=clk, clkdiv=clkdiv,
|
||||
name=f"des_{name}".strip("_"), **kwargs)
|
||||
self.submodules += Deserializer(**kwargs)
|
||||
|
||||
|
||||
class SimLogger(Module, AutoCSR):
|
||||
"""Logger for use in simulation
|
||||
|
||||
This module allows for easier message logging when running simulation designs.
|
||||
The logger can be used from `comb` context so it the methods can be directly
|
||||
used inside `FSM` code. It also provides logging levels that can be used to
|
||||
filter messages, either by specifying the default `log_level` or in runtime
|
||||
by driving to the `level` signal or using a corresponding CSR.
|
||||
"""
|
||||
# Allows to use Display inside FSM and to filter log messages by level (statically or dynamically)
|
||||
DEBUG = 0
|
||||
INFO = 1
|
||||
WARN = 2
|
||||
ERROR = 3
|
||||
NONE = 4
|
||||
|
||||
def __init__(self, log_level=INFO, clk_freq=None):
|
||||
self.ops = []
|
||||
self.level = Signal(reset=log_level, max=self.NONE)
|
||||
self.time_ps = None
|
||||
if clk_freq is not None:
|
||||
self.time_ps = Signal(64)
|
||||
cnt = Signal(64)
|
||||
self.sync += cnt.eq(cnt + 1)
|
||||
self.comb += self.time_ps.eq(cnt * int(1e12/clk_freq))
|
||||
|
||||
def debug(self, fmt, *args, **kwargs):
|
||||
return self.log("[DEBUG] " + fmt, *args, level=self.DEBUG, **kwargs)
|
||||
|
||||
def info(self, fmt, *args, **kwargs):
|
||||
return self.log("[INFO] " + fmt, *args, level=self.INFO, **kwargs)
|
||||
|
||||
def warn(self, fmt, *args, **kwargs):
|
||||
return self.log("[WARN] " + fmt, *args, level=self.WARN, **kwargs)
|
||||
|
||||
def error(self, fmt, *args, **kwargs):
|
||||
return self.log("[ERROR] " + fmt, *args, level=self.ERROR, **kwargs)
|
||||
|
||||
def log(self, fmt, *args, level=DEBUG, once=True):
|
||||
cond = Signal()
|
||||
if once: # make the condition be triggered only on rising edge
|
||||
condition = edge(self, cond)
|
||||
else:
|
||||
condition = cond
|
||||
|
||||
self.ops.append((level, condition, fmt, args))
|
||||
return cond.eq(1)
|
||||
|
||||
def add_csrs(self):
|
||||
self._level = CSRStorage(len(self.level), reset=self.level.reset.value)
|
||||
self.comb += self.level.eq(self._level.storage)
|
||||
|
||||
def do_finalize(self):
|
||||
for level, cond, fmt, args in self.ops:
|
||||
if self.time_ps is not None:
|
||||
fmt = f"[%16d ps] {fmt}"
|
||||
args = (self.time_ps, *args)
|
||||
self.sync += If((level >= self.level) & cond, Display(fmt, *args))
|
||||
|
||||
|
||||
class HoldValid(Module):
|
||||
"""Hold input data until ready
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue