sdram_init: add initial DDR4 initialization
This commit is contained in:
Florent Kermarrec
parent
8181fea0da
commit
ae5dc9f27a
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@ -318,8 +318,7 @@ class MT18KSF1G72HZ(SDRAMModule):
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class EDY4016A(SDRAMModule):
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memtype = "DDR4"
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# geometry
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nbanks_groups = 2
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nbanks = 4
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nbanks = 2*4 # 2 groups of 4 banks
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nrows = 32768
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ncols = 1024
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# timings
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@ -173,12 +173,8 @@ def get_sdram_phy_init_sequence(phy_settings, timing_settings):
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wr = max(timing_settings.tWTR*phy_settings.nphases, 5) # >= ceiling(tWR/tCK)
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mr0 = format_mr0(bl, cl, wr, 1)
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mr1 = format_mr1(
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z_to_ron[ron],
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z_to_rtt_nom[rtt_nom])
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mr2 = format_mr2(
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cwl,
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z_to_rtt_wr[rtt_wr])
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mr1 = format_mr1(z_to_ron[ron], z_to_rtt_nom[rtt_nom])
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mr2 = format_mr2(cwl, z_to_rtt_wr[rtt_wr])
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mr3 = 0
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init_sequence = [
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@ -190,6 +186,154 @@ def get_sdram_phy_init_sequence(phy_settings, timing_settings):
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("Load Mode Register 0, CL={0:d}, BL={1:d}".format(cl, bl), mr0, 0, cmds["MODE_REGISTER"], 200),
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("ZQ Calibration", 0x0400, 0, "DFII_COMMAND_WE|DFII_COMMAND_CS", 200),
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]
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elif phy_settings.memtype == "DDR4":
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bl = 8
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cwl = phy_settings.cwl
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def format_mr0(bl, cl, wr, dll_reset):
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bl_to_mr0 = {
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4: 0b10,
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8: 0b00
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}
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cl_to_mr0 = {
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9: 0b00000,
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10: 0b00001,
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11: 0b00010,
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12: 0b00011,
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13: 0b00100,
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14: 0b00101,
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15: 0b00110,
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16: 0b00111,
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18: 0b01000,
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20: 0b01001,
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22: 0b01010,
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24: 0b01011,
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23: 0b01100,
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17: 0b01101,
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19: 0b01110,
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21: 0b01111,
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25: 0b10000,
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26: 0b10001,
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27: 0b10010,
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28: 0b10011,
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29: 0b10100,
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30: 0b10101,
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31: 0b10110,
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32: 0b10111,
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}
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wr_to_mr0 = {
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10: 0b0000,
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12: 0b0001,
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14: 0b0010,
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16: 0b0011,
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18: 0b0100,
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20: 0b0101,
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24: 0b0110,
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22: 0b0111,
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26: 0b1000,
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28: 0b1001,
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}
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mr0 = bl_to_mr0[bl]
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mr0 |= (cl_to_mr0[cl] & 0b1) << 2
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mr0 |= ((cl_to_mr0[cl] >> 1) & 0b111) << 4
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mr0 |= ((cl_to_mr0[cl] >> 4) & 0b1) << 12
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mr0 |= dll_reset << 8
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mr0 |= (wr_to_mr0[wr] & 0b111) << 9
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mr0 |= (wr_to_mr0[wr] >> 3) << 13
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return mr0
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def format_mr1(ron, rtt_nom):
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mr1 = ((ron >> 0) & 0b1) << 1
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mr1 |= ((ron >> 1) & 0b1) << 2
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mr1 |= ((rtt_nom >> 0) & 0b1) << 8
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mr1 |= ((rtt_nom >> 1) & 0b1) << 9
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mr1 |= ((rtt_nom >> 2) & 0b1) << 10
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return mr1
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def format_mr2(cwl, rtt_wr):
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cwl_to_mr2 = {
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9: 0b000,
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10: 0b001,
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11: 0b010,
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12: 0b011,
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14: 0b100,
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16: 0b101,
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18: 0b110,
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20: 0b111
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}
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mr2 = cwl_to_mr2(cwl) << 3
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mr2 |= rtt_wr << 9
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return mr2
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def format_mr6(tccd):
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tccd_to_mr6 = {
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4: 0b000,
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5: 0b001,
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6: 0b010,
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7: 0b011,
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8: 0b100
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}
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mr6 = tccd_to_mr6[tccd] << 10
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return mr6
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z_to_rtt_nom = {
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"disabled" : 0b000,
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"60ohm" : 0b001,
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"120ohm" : 0b010,
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"40ohm" : 0b011,
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"240ohm" : 0b100,
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"48ohm" : 0b101,
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"80ohm" : 0b110,
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"34ohm" : 0b111
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}
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z_to_rtt_wr = {
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"disabled" : 0b000,
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"120ohm" : 0b001,
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"240ohm" : 0b010,
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"high-z" : 0b011,
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"80ohm" : 0b100,
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}
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z_to_ron = {
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"34ohm" : 0b00,
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"48ohm" : 0b01,
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}
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# default electrical settings (point to point)
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rtt_nom = "40ohm"
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rtt_wr = "120ohm"
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ron = "34ohm"
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# override electrical settings if specified
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if hasattr(phy_settings, "rtt_nom"):
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rtt_nom = phy_settings.rtt_nom
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if hasattr(phy_settings, "rtt_wr"):
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rtt_wr = phy_settings.rtt_wr
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if hasattr(phy_settings, "ron"):
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ron = phy_settings.ron
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wr = max(timing_settings.tWTR*phy_settings.nphases, 5) # >= ceiling(tWR/tCK)
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mr0 = format_mr0(bl, cl, wr, 1)
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mr1 = format_mr1(z_to_ron[ron], z_to_rtt_nom[rtt_nom])
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mr2 = format_mr2(cwl, z_to_rtt_wr(rtt_wr))
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mr3 = 0
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mr4 = 0
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mr5 = 0
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mr6 = format_mr6(4) # FIXME: tCCD
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init_sequence = [
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("Release reset", 0x0000, 0, cmds["UNRESET"], 50000),
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("Bring CKE high", 0x0000, 0, cmds["CKE"], 10000),
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("Load Mode Register 3", mr3, 3, cmds["MODE_REGISTER"], 0),
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("Load Mode Register 6", mr6, 6, cmds["MODE_REGISTER"], 0),
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("Load Mode Register 5", mr5, 5, cmds["MODE_REGISTER"], 0),
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("Load Mode Register 4", mr4, 4, cmds["MODE_REGISTER"], 0),
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("Load Mode Register 2, CWL={0:d}".format(cwl), mr2, 2, cmds["MODE_REGISTER"], 0),
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("Load Mode Register 1", mr1, 1, cmds["MODE_REGISTER"], 0),
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("Load Mode Register 0, CL={0:d}, BL={1:d}".format(cl, bl), mr0, 0, cmds["MODE_REGISTER"], 200),
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("ZQ Calibration", 0x0400, 0, "DFII_COMMAND_WE|DFII_COMMAND_CS", 200),
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]
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else:
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raise NotImplementedError("Unsupported memory type: " + phy_settings.memtype)
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