gen: Add option to specify CSR alignment

On some standalone core implementations, such with Microwatt,
the main system bus is 64-bit, but the wishbone to access the
CSRs is 32-bit.

To avoid extra logic & muxes and just wire these together, it's
useful to be able to specify a larger alignemnt (64-bit) for the
CSRs so that the generated csr.h contains the right offsets.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

litedram/gen.py

@@ -304,6 +304,7 @@ class LiteDRAMCore(SoCCore):
         cpu_type     = core_config["cpu"]
         cpu_variant  = core_config.get("cpu_variant",  "standard")
         had_ddrctl   = core_config.get("has_ddrctl", False)
+        csr_align    = core_config.get("csr_align", 32)
         if cpu_type is None:
             kwargs["integrated_rom_size"]  = 0
             kwargs["integrated_sram_size"] = 0
@@ -317,6 +318,7 @@ class LiteDRAMCore(SoCCore):
             cpu_type      = cpu_type,
             cpu_variant   = cpu_variant,
             csr_base      = csr_base,
+            csr_alignment = csr_align,
             **kwargs)
 
         # CRG --------------------------------------------------------------------------------------