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phy/s7ddrphy: handle cmd_latency properly (add it to rd/wrphase).

This commit is contained in:
Florent Kermarrec 2020-09-30 19:40:55 +02:00
parent 05ed5bf59d
commit b1c26d996f
1 changed files with 6 additions and 7 deletions
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13
litedram/phy/s7ddrphy.py
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@ -50,12 +50,11 @@ class S7DDRPHY(Module, AutoCSR):
} }
half_sys8x_taps = math.floor(tck/(4*iodelay_tap_average[iodelay_clk_freq])) half_sys8x_taps = math.floor(tck/(4*iodelay_tap_average[iodelay_clk_freq]))
cl, cwl = get_cl_cw(memtype, tck) cl, cwl = get_cl_cw(memtype, tck)
cl_sys_latency = get_sys_latency(nphases, cl) cl_sys_latency = get_sys_latency(nphases, cl)
cwl = cwl + cmd_latency cwl_sys_latency = get_sys_latency(nphases, cwl)
cwl_sys_latency = get_sys_latency(nphases, cwl) rdphase = get_sys_phase(nphases, cl_sys_latency, cl + cmd_latency)
rdcmdphase, rdphase = get_sys_phases(nphases, cl_sys_latency, cl) wrphase = get_sys_phase(nphases, cwl_sys_latency, cwl + cmd_latency)
wrcmdphase, wrphase = get_sys_phases(nphases, cwl_sys_latency, cwl)
# Registers -------------------------------------------------------------------------------- # Registers --------------------------------------------------------------------------------
self._rst = CSRStorage() self._rst = CSRStorage()
@ -106,7 +105,7 @@ class S7DDRPHY(Module, AutoCSR):
rdcmdphase = _rdcmdphase, rdcmdphase = _rdcmdphase,
wrcmdphase = _wrcmdphase, wrcmdphase = _wrcmdphase,
cl = cl, cl = cl,
cwl = cwl - cmd_latency, cwl = cwl,
read_latency = cl_sys_latency + 6, read_latency = cl_sys_latency + 6,
write_latency = cwl_sys_latency, write_latency = cwl_sys_latency,
cmd_latency = cmd_latency, cmd_latency = cmd_latency,