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frontend/bist: only use cdc on registers if needed (ie not in sys clock domain)

This commit is contained in:
Florent Kermarrec 2018-08-28 18:59:56 +02:00
parent 92c8513598
commit b1e734b2ac
1 changed files with 99 additions and 74 deletions
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25
litedram/frontend/bist.py
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@ -230,6 +230,7 @@ class LiteDRAMBISTGenerator(Module, AutoCSR):
core = ClockDomainsRenamer(clock_domain)(core)
self.submodules += core
if clock_domain != "sys":
reset_sync = PulseSynchronizer("sys", clock_domain)
start_sync = PulseSynchronizer("sys", clock_domain)
self.submodules += reset_sync, start_sync
@ -270,6 +271,17 @@ class LiteDRAMBISTGenerator(Module, AutoCSR):
ticks_sync.i.eq(core.ticks),
self.ticks.status.eq(ticks_sync.o)
]
else:
self.comb += [
core.reset.eq(self.reset.re),
core.start.eq(self.start.re),
self.done.status.eq(core.done),
core.base.eq(self.base.storage),
core.length.eq(self.length.storage),
core.random_data_enable.eq(self.random_data_enable.storage),
core.random_addr_enable.eq(self.random_addr_enable.storage),
self.ticks.status.eq(core.ticks)
]
@ResetInserter()
@ -412,6 +424,7 @@ class LiteDRAMBISTChecker(Module, AutoCSR):
core = ClockDomainsRenamer(clock_domain)(core)
self.submodules += core
if clock_domain != "sys":
reset_sync = PulseSynchronizer("sys", clock_domain)
start_sync = PulseSynchronizer("sys", clock_domain)
self.submodules += reset_sync, start_sync
@ -459,3 +472,15 @@ class LiteDRAMBISTChecker(Module, AutoCSR):
errors_sync.i.eq(core.errors),
self.errors.status.eq(errors_sync.o)
]
else:
self.comb += [
core.reset.eq(self.reset.re),
core.start.eq(self.start.re),
self.done.status.eq(core.done),
core.base.eq(self.base.storage),
core.length.eq(self.length.storage),
core.random_data_enable.eq(self.random_data_enable.storage),
core.random_addr_enable.eq(self.random_addr_enable.storage),
self.ticks.status.eq(core.ticks),
self.errors.status.eq(core.errors)
]