Merge pull request #105 from ximinity/gen_ecp5
WIP: litedram_gen: add ecp5 support
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enjoy-digital
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b1f087959b
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@ -3,6 +3,7 @@
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{
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# General ------------------------------------------------------------------
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"platform": "xilinx", # Platform type
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"cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32)
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"speedgrade": -1, # FPGA speedgrade
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"memtype": "DDR3", # DRAM type
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@ -3,6 +3,7 @@
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{
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# General ------------------------------------------------------------------
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"platform": "xilinx", # Platform type
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"cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32)
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"speedgrade": -2, # FPGA speedgrade
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"memtype": "DDR3", # DRAM type
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@ -3,6 +3,7 @@
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{
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# General ------------------------------------------------------------------
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"platform": "xilinx", # Platform type
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"cpu": "vexriscv", # Type of CPU used for init/calib (vexriscv, lm32)
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"speedgrade": -1, # FPGA speedgrade
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"memtype": "DDR2", # DRAM type
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@ -0,0 +1,45 @@
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# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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{
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# General ------------------------------------------------------------------
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"platform": "ecp5", # Platform type
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"cpu": None, # Type of CPU used for init/calib (vexriscv, lm32)
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# PHY ----------------------------------------------------------------------
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"sdram_module": "MT41K64M16", # SDRAM modules of the board or SO-DIMM
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"sdram_module_nb": 2, # Number of byte groups
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"sdram_rank_nb": 1, # Number of ranks
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"sdram_phy": "ECP5DDRPHY", # Type of FPGA PHY
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# Frequency ----------------------------------------------------------------
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"input_clk_freq": 100e6, # Input clock frequency
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"sys_clk_freq": 50e6, # System clock frequency (DDR_clk = 4 x sys_clk)
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"init_clk_freq": 25e6, # Init clock frequency
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# Core ---------------------------------------------------------------------
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"cmd_buffer_depth": 16, # Depth of the command buffer
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# User Ports ---------------------------------------------------------------
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"user_ports": {
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"axi_0" : {
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"type": "axi",
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"id_width": 32,
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},
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"wishbone_0" : {
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"type": "wishbone",
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},
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"native_0" : {
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"type": "native",
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},
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"fifo_0" : {
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"type": "fifo",
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"base": 0x00000000,
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"depth": 0x01000000,
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},
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},
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# CSR Port -----------------------------------------------------------------
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"csr_expose": "False", # Expose CSR bus as I/Os
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"csr_align" : 32, # CSR alignment
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}
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@ -16,7 +16,8 @@ for some use cases it could be interesting to generate a standalone verilog file
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The standalone core is generated from a YAML configuration file that allows the user to generate
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easily a custom configuration of the core.
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Current version of the generator is limited to Xilinx 7-Series FPGA for DDR2/DDR3 memories.
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Current version of the generator is limited to Xilinx 7-Series FPGA for
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DDR2/DDR3 memories and the versa ECP5-5G.
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"""
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import os
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@ -31,6 +32,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform
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from litex.boards.platforms import versa_ecp5
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_sdram import *
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@ -247,6 +249,50 @@ class LiteDRAMCRG(Module):
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iodelay_pll.create_clkout(self.cd_iodelay, core_config["iodelay_clk_freq"])
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self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_iodelay)
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class LatticeDRAMCRG(Module):
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def __init__(self, platform, core_config):
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self.clock_domains.cd_init = ClockDomain()
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self.clock_domains.cd_por = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys2x = ClockDomain()
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self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
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# # #
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self.stop = Signal()
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# clk / rst
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clk100 = platform.request("clk100")
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rst_n = platform.request("rst_n")
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platform.add_period_constraint(clk100, 10.0)
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# power on reset
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por_count = Signal(16, reset=2**16-1)
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por_done = Signal()
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self.comb += self.cd_por.clk.eq(ClockSignal())
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self.comb += por_done.eq(por_count == 0)
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self.sync.por += If(~por_done, por_count.eq(por_count - 1))
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# pll
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self.submodules.pll = pll = ECP5PLL()
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pll.register_clkin(clk100, core_config['sys_clk_freq'])
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pll.create_clkout(self.cd_sys2x_i, 2*core_config["sys_clk_freq"])
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pll.create_clkout(self.cd_init, core_config['init_clk_freq'])
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self.specials += [
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Instance("ECLKSYNCB",
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i_ECLKI=self.cd_sys2x_i.clk,
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i_STOP=self.stop,
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o_ECLKO=self.cd_sys2x.clk),
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Instance("CLKDIVF",
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p_DIV="2.0",
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i_ALIGNWD=0,
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i_CLKI=self.cd_sys2x.clk,
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i_RST=self.cd_sys2x.rst,
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o_CDIVX=self.cd_sys.clk),
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AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked | ~rst_n),
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AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | ~rst_n)
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]
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# LiteDRAMCoreControl ------------------------------------------------------------------------------
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class LiteDRAMCoreControl(Module, AutoCSR):
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@ -278,7 +324,7 @@ class LiteDRAMCore(SoCSDRAM):
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kwargs["with_uart"] = False
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kwargs["with_timer"] = False
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kwargs["with_ctrl"] = False
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kwargs["with_wishbone"] = (cpu_type != None)
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kwargs["with_wishbone"] = False
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else:
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kwargs["l2_size"] = 0
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kwargs["min_l2_data_width"] = 0
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@ -290,6 +336,24 @@ class LiteDRAMCore(SoCSDRAM):
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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if core_config["platform"] == "ecp5":
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crg = LatticeDRAMCRG(platform, core_config)
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self.submodules.crg = crg
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self.submodules.ddrphy = core_config["sdram_phy"](
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platform.request("ddram"),
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sys_clk_freq=sys_clk_freq)
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self.comb += crg.stop.eq(self.ddrphy.init.stop)
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sdram_module = core_config["sdram_module"](sys_clk_freq, "1:2")
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controller_settings = controller_settings=ControllerSettings(
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cmd_buffer_depth=core_config["cmd_buffer_depth"])
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self.register_sdram(self.ddrphy,
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sdram_module.geom_settings,
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sdram_module.timing_settings,
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controller_settings=controller_settings)
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else:
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self.submodules.crg = LiteDRAMCRG(platform, core_config)
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# DRAM -------------------------------------------------------------------------------------
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@ -502,6 +566,13 @@ def main():
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# Generate core --------------------------------------------------------------------------------
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platform = Platform()
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if core_config["platform"] == "ecp5":
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platform = versa_ecp5.Platform(toolchain="trellis")
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elif core_config["platform"] == "xilinx":
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platform = XilinxPlatform("", io=[], toolchain="vivado")
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else:
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raise ValueError("Unknown platform specified in {}".format(args.config));
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soc = LiteDRAMCore(platform, core_config, integrated_rom_size=0x6000, integrated_sram_size=0x1000)
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builder = Builder(soc, output_dir="build", compile_gateware=False)
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vns = builder.build(build_name="litedram_core", regular_comb=False)
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