test: add bist_async_tb and some fixes

litedram/frontend/bist.py

@@ -145,7 +145,7 @@ class _LiteDRAMBISTChecker(Module, AutoCSR):
 
         self.comb += [
             dma.sink.valid.eq(address_enable),
-            dma.sink.address.eq(self.base + address_counter),
+            dma.sink.address.eq(self.base + address_counter - 1),
             address_counter_ce.eq(address_enable & dma.sink.ready)
         ]
 
@@ -191,7 +191,7 @@ class LiteDRAMBISTChecker(Module, AutoCSR):
         base_sync = BusSynchronizer(dram_port.aw, "sys", cd)
         length_sync = BusSynchronizer(dram_port.aw, "sys", cd)
         error_count_sync = BusSynchronizer(32, cd, "sys")
-        self.submodules += base_sync, length_sync
+        self.submodules += base_sync, length_sync, error_count_sync
 
         self.comb += [
             reset_sync.i.eq(self.reset.re),

litedram/frontend/crossbar.py

@@ -13,11 +13,11 @@ class LiteDRAMAsyncAdapter(Module):
         aw = port_from.aw
         dw = port_from.dw
         cd_from = port_from.cd
-        cd_to = port_from.cd
+        cd_to = port_to.cd
 
         # # #
 
-        cmd_fifo = stream.AsyncFIFO([("we", 1), ("adr", aw)], 4)
+        cmd_fifo = stream.AsyncFIFO([("we", 1), ("adr", aw)], 8)
         cmd_fifo = ClockDomainsRenamer({"write": cd_from, "read": cd_to})(cmd_fifo)
         self.submodules += cmd_fifo
         self.comb += [
@@ -25,7 +25,7 @@ class LiteDRAMAsyncAdapter(Module):
             cmd_fifo.source.connect(port_to.cmd)
         ]
 
-        wdata_fifo = stream.AsyncFIFO([("data", dw), ("we", dw//8)], 4)
+        wdata_fifo = stream.AsyncFIFO([("data", dw), ("we", dw//8)], 8)
         wdata_fifo = ClockDomainsRenamer({"write": cd_from, "read": cd_to})(wdata_fifo)
         self.submodules += wdata_fifo
         self.comb += [
@@ -33,12 +33,12 @@ class LiteDRAMAsyncAdapter(Module):
             wdata_fifo.source.connect(port_to.wdata)
         ]
 
-        rdata_fifo = stream.AsyncFIFO([("data", dw)], 4)
+        rdata_fifo = stream.AsyncFIFO([("data", dw)], 8)
         rdata_fifo = ClockDomainsRenamer({"write": cd_to, "read": cd_from})(rdata_fifo)
         self.submodules += rdata_fifo
         self.comb += [
-            port_to.rdata.connect(rddata_fifo.sink),
+            port_to.rdata.connect(rdata_fifo.sink),
-            rddata_fifo.source.connect(port_from.rdata)
+            rdata_fifo.source.connect(port_from.rdata)
         ]
 
 

test/Makefile

@@ -6,4 +6,7 @@ CMD = PYTHONPATH=$(COREDIR) $(PYTHON)
 bist_tb:
 	$(CMD) bist_tb.py
 
-all: bist_tb
+bist_async_tb:
+	$(CMD) bist_async_tb.py
+
+all: bist_tb bist_async_tb

test/bist_async_tb.py

@@ -0,0 +1,97 @@
+from litex.gen import *
+
+from litex.soc.interconnect.stream import *
+
+from litedram.common import PhySettings, LiteDRAMPort
+from litedram.core import *
+from litedram.modules import SDRAMModule
+from litedram.frontend.crossbar import LiteDRAMCrossbar
+from litedram.frontend.bist import LiteDRAMBISTGenerator
+from litedram.frontend.bist import LiteDRAMBISTChecker
+
+from litedram.phy.model import SDRAMPHYModel
+
+class SimModule(SDRAMModule):
+    # geometry
+    nbanks = 4
+    nrows  = 2048
+    ncols  = 4
+    # timings
+    tRP   = 1
+    tRCD  = 1
+    tWR   = 1
+    tWTR  = 1
+    tREFI = 1
+    tRFC  = 1
+
+
+class TB(Module):
+    def __init__(self):
+        sdram_module = SimModule(1000, "1:1")
+        phy_settings = PhySettings(
+            memtype="SDR",
+            dfi_databits=1*16,
+            nphases=1,
+            rdphase=0,
+            wrphase=0,
+            rdcmdphase=0,
+            wrcmdphase=0,
+            cl=2,
+            read_latency=4,
+            write_latency=0
+        )
+        self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings)
+        self.submodules.controller = LiteDRAMController(
+                                         phy_settings,
+                                         sdram_module.geom_settings,
+                                         sdram_module.timing_settings,
+                                         ControllerSettings(with_refresh=False))
+        self.comb += self.controller.dfi.connect(self.sdrphy.dfi)
+        self.submodules.crossbar = LiteDRAMCrossbar(self.controller.interface,
+                                                    self.controller.nrowbits)
+        self.write_port = self.crossbar.get_port(cd="write")
+        self.read_port = self.crossbar.get_port(cd="read")
+        self.submodules.generator = LiteDRAMBISTGenerator(self.write_port, cd="write")
+        self.submodules.checker = LiteDRAMBISTChecker(self.read_port, cd="read")
+
+
+def main_generator(dut):
+    for i in range(100):
+        yield
+    # write
+    yield dut.generator.base.storage.eq(16)
+    yield dut.generator.length.storage.eq(16)
+    for i in range(32):
+        yield
+    yield dut.generator.shoot.re.eq(1)
+    yield
+    yield dut.generator.shoot.re.eq(0)
+    for i in range(32):
+        yield
+    while((yield dut.generator.done.status) == 0):
+        yield
+    # read
+    yield dut.checker.base.storage.eq(16)
+    yield dut.checker.length.storage.eq(16)
+    for i in range(32):
+        yield
+    yield dut.checker.shoot.re.eq(1)
+    yield
+    yield dut.checker.shoot.re.eq(0)
+    for i in range(32):
+        yield
+    while((yield dut.checker.done.status) == 0):
+        yield
+    # check
+    print("errors {:d}".format((yield dut.checker.error_count.status)))
+    yield
+
+if __name__ == "__main__":
+    tb = TB()
+    generators = {
+        "sys" :   [main_generator(tb)]
+    }
+    clocks = {"sys":   10,
+              "write": 12,
+              "read":   8}
+    run_simulation(tb, generators, clocks, vcd_name="sim.vcd")

test/bist_tb.py

@@ -16,7 +16,7 @@ class TB(Module):
         self.submodules.checker = LiteDRAMBISTChecker(self.read_port)
 
 def main_generator(dut):
-    for i in range(100):
+    for i in range(8):
         yield
     # write
     yield dut.generator.base.storage.eq(16)