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core/controller: add separators, ease readibility

This commit is contained in:
Florent Kermarrec 2019-08-16 08:34:22 +02:00
parent 338d18dba0
commit b64daba711
2 changed files with 41 additions and 28 deletions
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4
litedram/core/bankmachine.py
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@ -25,8 +25,8 @@ class _AddressSlicer:
class BankMachine(Module): class BankMachine(Module):
def __init__(self, n, aw, address_align, nranks, settings): def __init__(self, n, address_width, address_align, nranks, settings):
self.req = req = Record(cmd_layout(aw)) self.req = req = Record(cmd_layout(address_width))
self.refresh_req = refresh_req = Signal() self.refresh_req = refresh_req = Signal()
self.refresh_gnt = refresh_gnt = Signal() self.refresh_gnt = refresh_gnt = Signal()

65
litedram/core/controller.py
View File

@ -7,10 +7,11 @@ from migen import *
from litedram.common import * from litedram.common import *
from litedram.phy import dfi from litedram.phy import dfi
from litedram.core.refresher import * from litedram.core.refresher import Refresher
from litedram.core.bankmachine import * from litedram.core.bankmachine import BankMachine
from litedram.core.multiplexer import * from litedram.core.multiplexer import Multiplexer
# Settings -----------------------------------------------------------------------------------------
class ControllerSettings(Settings): class ControllerSettings(Settings):
def __init__(self, def __init__(self,
@ -22,45 +23,57 @@ class ControllerSettings(Settings):
address_mapping="ROW_BANK_COL"): address_mapping="ROW_BANK_COL"):
self.set_attributes(locals()) self.set_attributes(locals())
# Controller ---------------------------------------------------------------------------------------
class LiteDRAMController(Module): class LiteDRAMController(Module):
def __init__(self, phy_settings, geom_settings, timing_settings, def __init__(self, phy_settings, geom_settings, timing_settings,
controller_settings=ControllerSettings()): controller_settings=ControllerSettings()):
address_align = log2_int(burst_lengths[phy_settings.memtype]) address_align = log2_int(burst_lengths[phy_settings.memtype])
self.settings = settings = controller_settings
self.settings.phy = phy_settings # Settings ---------------------------------------------------------------------------------
self.settings.geom = geom_settings self.settings = controller_settings
self.settings.phy = phy_settings
self.settings.geom = geom_settings
self.settings.timing = timing_settings self.settings.timing = timing_settings
self.dfi = dfi.Interface( nranks = phy_settings.nranks
geom_settings.addressbits, nbanks = 2**geom_settings.bankbits
geom_settings.bankbits,
phy_settings.nranks,
phy_settings.dfi_databits,
phy_settings.nphases)
self.interface = interface = LiteDRAMInterface(address_align, settings) # LiteDRAM Interface (User) ----------------------------------------------------------------
self.interface = interface = LiteDRAMInterface(address_align, self.settings)
# DFI Interface (Memory) -------------------------------------------------------------------
self.dfi = dfi.Interface(
addressbits = geom_settings.addressbits,
bankbits = geom_settings.bankbits,
nranks = phy_settings.nranks,
databits = phy_settings.dfi_databits,
nphases = phy_settings.nphases)
# # # # # #
# refresher # Refresher --------------------------------------------------------------------------------
self.submodules.refresher = Refresher(settings) self.submodules.refresher = Refresher(self.settings)
# bank machines # Bank Machines ----------------------------------------------------------------------------
bank_machines = [] bank_machines = []
for i in range(phy_settings.nranks*(2**geom_settings.bankbits)): for n in range(nranks*nbanks):
bank_machine = BankMachine(i, bank_machine = BankMachine(n,
interface.address_width, address_width = interface.address_width,
address_align, address_align = address_align,
phy_settings.nranks, nranks = nranks,
settings) settings = self.settings)
bank_machines.append(bank_machine) bank_machines.append(bank_machine)
self.submodules += bank_machine self.submodules += bank_machine
self.comb += getattr(interface, "bank"+str(i)).connect(bank_machine.req) self.comb += getattr(interface, "bank"+str(n)).connect(bank_machine.req)
# multiplexer # Multiplexer ------------------------------------------------------------------------------
self.submodules.multiplexer = Multiplexer( self.submodules.multiplexer = Multiplexer(
settings, bank_machines, self.refresher, self.dfi, interface) settings = self.settings,
bank_machines = bank_machines,
refresher = self.refresher,
dfi = self.dfi,
interface = interface)
def get_csrs(self): def get_csrs(self):
return self.multiplexer.get_csrs() return self.multiplexer.get_csrs()