frontend/crossbar: add skeleton/descroption for port downconverters/upconverters
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@ -8,8 +8,12 @@ from litex.soc.interconnect import stream
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from litedram.common import *
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class LiteDRAMAsyncAdapter(Module):
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def __init__(self, port_from, port_to):
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assert port_from.aw == port_to.aw
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assert port_from.dw == port.to.dw
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aw = port_from.aw
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dw = port_from.dw
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cd_from = port_from.cd
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@ -42,6 +46,54 @@ class LiteDRAMAsyncAdapter(Module):
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]
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class _LiteDRAMDownConverter(Module):
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"""LiteDRAM port DownConverter
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This module reduces user port data width to fit controller data width.
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With N = port_from.dw/port_to.dw:
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- Address is adapted (multiplied by N + internal increments)
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- A single write from the user is splitted and generate N writes to the
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controller.
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- Reads generates N reads on the controller and returned datas are regroup
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into a single data presented to the user.
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"""
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def __init__(self, port_from, port_to):
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assert port_from.cd == port_to.cd
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assert port_from.dw > port_to.dw
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# # #
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class _LiteDRAMUpConverter(Module):
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"""LiteDRAM port UpConverter
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This module increase user port data width to fit controller data width.
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With N = port_to.dw/port_from.dw:
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- Address is adapted (divided by N)
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- N writes and read from user are regrouped in a single one to the controller
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(when possible, ie when consecutive and bursting)
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"""
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def __init__(self, port_from, port_to):
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assert port_from.cd == port_to.cd
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assert port_from.dw < port_to.dw
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# # #
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class LiteDRAMConverter(Module):
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def __init__(self, port_from, port_to):
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assert port_from.cd == port_to.cd
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# # #
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if port_from.dw > port_to.dw:
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converter = _LiteDRAMDownConverter(port_from, port_to)
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self.submodules += converter
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elif port_from.dw < port.to.dw:
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converter = _LiteDRAMUpConverter(port_from, port_to)
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self.submodules += converter
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class LiteDRAMCrossbar(Module):
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def __init__(self, controller, cba_shift):
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self.controller = controller
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