Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

phy/lpddr5/sim: make adding module loggers simpler

This commit is contained in:
Jędrzej Boczar 2021-07-09 14:49:48 +02:00 committed by Alessandro Comodi
parent 5544875e1d
commit b8616fdfac
3 changed files with 14 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
litedram/phy/lpddr5/sim.py
View File

@ -53,10 +53,10 @@ class LPDDR5Sim(Module, AutoCSR):
cmd_info = stream.Endpoint(CMD_INFO_LAYOUT)
gtkw_dbg["cmd_info"] = cmd_info
cmd = CommandsSim(pads, cmd_info, logger_kwargs=logger_kwargs, log_level=log_level("cmd"))
cmd = CommandsSim(pads, cmd_info, logger_kwargs=logger_kwargs, log_level=log_level)
self.submodules.cmd = ClockDomainsRenamer("ck")(cmd)
data = DataSim(pads, cmd_info, cmd.data_timer.ready_p, logger_kwargs=logger_kwargs, log_level=log_level("data"))
data = DataSim(pads, cmd_info, cmd.data_timer.ready_p, logger_kwargs=logger_kwargs, log_level=log_level)
self.submodules.data = ClockDomainsRenamer("wck")(data)
@ -142,8 +142,7 @@ class ModeRegisters(Module, AutoCSR):
)
def __init__(self, *, log_level, logger_kwargs):
self.submodules.log = log = SimLogger(log_level=log_level, **logger_kwargs)
self.log.add_csrs()
self.submodules.log = SimLogger(log_level=log_level("mr"), **logger_kwargs)
self.mr = Array([
Signal(8, reset=self.MR_RESET.get(addr, 0), name=f"mr{addr}")
@ -219,8 +218,7 @@ class Sync(list):
class CommandsSim(Module, AutoCSR):
def __init__(self, pads, cmd_info, *, log_level, logger_kwargs):
self.submodules.log = log = SimLogger(log_level=log_level, **logger_kwargs)
self.log.add_csrs()
self.submodules.log = SimLogger(log_level=log_level("cmd"), **logger_kwargs)
self.comb += self.log.info("Simulation start")
self.cmd_info = cmd_info
@ -498,8 +496,7 @@ class CommandsSim(Module, AutoCSR):
class DataSim(Module, AutoCSR):
def __init__(self, pads, cmd_info, latency_ready, *, log_level, logger_kwargs, nrows=32768, ncols=1024, nbanks=16):
self.submodules.log = log = SimLogger(log_level=log_level, **logger_kwargs)
self.log.add_csrs()
self.submodules.log = SimLogger(log_level=log_level("data"), **logger_kwargs)
# CommandsSim produces the data required for handling a data command via cmd_info endpoint.
# Using stream.ClockDomainCrossing introduces too much latency, so we do a simplistic CDC

8
litedram/phy/lpddr5/simsoc.py
View File

@ -140,7 +140,11 @@ class SimSoC(SoCCore):
self.submodules.lpddr5sim = LPDDR5Sim(
pads = self.ddrphy.pads,
log_level = log_level,
logger_kwargs = dict(clk_freq_cd=f"sys{2*wck_ck_ratio}x", clk_freq=2*wck_ck_ratio * sys_clk_freq),
logger_kwargs = dict(
clk_freq_cd = f"sys{2*wck_ck_ratio}x",
clk_freq = 2*wck_ck_ratio * sys_clk_freq,
with_csrs = True,
),
)
self.add_constant("CONFIG_SIM_DISABLE_BIOS_PROMPT")
@ -277,7 +281,7 @@ def generate_gtkw_savefile(builder, vns, trace_fst):
)
from litedram.phy.lpddr5.sim import gtkw_dbg
for name in "cmd_info cmds cmd_buf current_cmd".split():
for name in "cmd_info cmd_buf".split():
save.add(gtkw_dbg[name], group_name=name, closed=False,
# mappers=[gtkw.endpoint_filter(payload=False)],
mappers=[gtkw.endpoint_filter()],

4
litedram/phy/sim_utils.py
View File

@ -151,7 +151,7 @@ class SimLogger(Module, AutoCSR):
ERROR = 3
NONE = 4
def __init__(self, log_level=INFO, clk_freq=None, clk_freq_cd=None):
def __init__(self, log_level=INFO, clk_freq=None, clk_freq_cd=None, with_csrs=False):
self.ops = []
self.level = Signal(reset=log_level, max=self.NONE + 1)
self.time_ps = None
@ -161,6 +161,8 @@ class SimLogger(Module, AutoCSR):
sd_cnt = self.sync if clk_freq_cd is None else getattr(self.sync, clk_freq_cd)
sd_cnt += cnt.eq(cnt + 1)
self.comb += self.time_ps.eq(cnt * int(1e12/clk_freq))
if with_csrs:
self.add_csrs()
def debug(self, fmt, *args, **kwargs):
return self.log("[DEBUG] " + fmt, *args, level=self.DEBUG, **kwargs)