frontend/axi: remove write buffer reservation (not needed)
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@ -145,8 +145,6 @@ class LiteDRAMAXI2NativeW(Module):
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# # #
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# # #
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can_write = Signal()
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ashift = log2_int(port.data_width//8)
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ashift = log2_int(port.data_width//8)
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# Burst to Beat
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# Burst to Beat
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@ -160,9 +158,6 @@ class LiteDRAMAXI2NativeW(Module):
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w_buffer = stream.SyncFIFO(w_description(axi.data_width), buffer_depth)
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w_buffer = stream.SyncFIFO(w_description(axi.data_width), buffer_depth)
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self.submodules += w_buffer
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self.submodules += w_buffer
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# Write Buffer reservation
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self.comb += can_write.eq(w_buffer.sink.ready)
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# Write ID Buffer & Response
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# Write ID Buffer & Response
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id_buffer = stream.SyncFIFO([("id", axi.id_width)], buffer_depth)
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id_buffer = stream.SyncFIFO([("id", axi.id_width)], buffer_depth)
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resp_buffer = stream.SyncFIFO([("id", axi.id_width), ("resp", 2)], buffer_depth)
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resp_buffer = stream.SyncFIFO([("id", axi.id_width), ("resp", 2)], buffer_depth)
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@ -181,10 +176,10 @@ class LiteDRAMAXI2NativeW(Module):
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# Command
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# Command
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self.comb += [
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self.comb += [
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self.cmd_request.eq(aw.valid & can_write),
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self.cmd_request.eq(aw.valid),
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If(self.cmd_grant,
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If(self.cmd_grant,
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port.cmd.valid.eq(aw.valid & can_write),
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port.cmd.valid.eq(aw.valid),
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aw.ready.eq(port.cmd.ready & can_write),
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aw.ready.eq(port.cmd.ready),
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port.cmd.we.eq(1),
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port.cmd.we.eq(1),
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port.cmd.addr.eq(aw.addr >> ashift)
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port.cmd.addr.eq(aw.addr >> ashift)
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)
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)
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