test/test_init: use max_sdram_size of 1GB
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@ -36,7 +36,7 @@ class TestInit(unittest.TestCase):
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def test_ddr4(self):
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def test_ddr4(self):
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from litex.boards.targets.kcu105 import BaseSoC
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from litex.boards.targets.kcu105 import BaseSoC
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soc = BaseSoC()
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soc = BaseSoC(max_sdram_size=0x4000000)
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c_header = get_sdram_phy_c_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)
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c_header = get_sdram_phy_c_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)
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py_header = get_sdram_phy_py_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)
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py_header = get_sdram_phy_py_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)
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self.assertEqual(compare_with_reference(c_header, "ddr4_init.h"), True)
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self.assertEqual(compare_with_reference(c_header, "ddr4_init.h"), True)
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