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frontend/axi: use definitions from LiteX

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AXI definitions were not present in LiteX when AXI support was added to LiteDRAM.
This commit is contained in:
Florent Kermarrec 2019-04-19 11:57:05 +02:00
parent e81b5a11b8
commit be269da3fe
2 changed files with 19 additions and 69 deletions
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72
litedram/frontend/axi.py
View file

@ -19,62 +19,11 @@ from migen.genlib.record import *
from migen.genlib.roundrobin import *
from litex.soc.interconnect import stream
burst_types = {
"fixed": 0b00,
"incr": 0b01,
"wrap": 0b10,
"reserved": 0b11
}
resp_types = {
"okay": 0b00,
"exokay": 0b01,
"slverr": 0b10,
"decerr": 0b11
}
def ax_description(address_width, id_width):
return [
("addr", address_width),
("burst", 2), # Burst type
("len", 8), # Number of data (-1) transfers (up to 256)
("size", 4), # Number of bytes (-1) of each data transfer (up to 1024 bits)
("id", id_width)
]
def w_description(data_width):
return [
("data", data_width),
("strb", data_width//8)
]
def b_description(id_width):
return [
("resp", 2),
("id", id_width)
]
def r_description(data_width, id_width):
return [
("resp", 2),
("data", data_width),
("id", id_width)
]
from litex.soc.interconnect.axi import *
class LiteDRAMAXIPort(Record):
def __init__(self, data_width, address_width, id_width=1, clock_domain="sys"):
self.data_width = data_width
self.address_width = address_width
self.id_width = id_width
self.clock_domain = clock_domain
self.aw = stream.Endpoint(ax_description(address_width, id_width))
self.w = stream.Endpoint(w_description(data_width))
self.b = stream.Endpoint(b_description(id_width))
self.ar = stream.Endpoint(ax_description(address_width, id_width))
self.r = stream.Endpoint(r_description(data_width, id_width))
class LiteDRAMAXIPort(AXIInterface):
pass
class LiteDRAMAXIBurst2Beat(Module):
@ -117,8 +66,8 @@ class LiteDRAMAXIBurst2Beat(Module):
ax_beat.valid.eq(1),
ax_beat.first.eq(0),
ax_beat.last.eq(count == ax_burst.len),
If((ax_burst.burst == burst_types["incr"]) |
(ax_burst.burst == burst_types["wrap"]),
If((ax_burst.burst == BURST_INCR) |
(ax_burst.burst == BURST_WRAP),
ax_beat.addr.eq(ax_burst.addr + offset)
).Else(
ax_beat.addr.eq(ax_burst.addr)
@ -131,7 +80,7 @@ class LiteDRAMAXIBurst2Beat(Module):
),
NextValue(count, count + 1),
NextValue(offset, offset + size),
If(ax_burst.burst == burst_types["wrap"],
If(ax_burst.burst == BURST_WRAP,
If(offset == wrap_offset,
NextValue(offset, 0)
)
@ -158,7 +107,8 @@ class LiteDRAMAXI2NativeW(Module):
self.submodules.aw_burst2beat = aw_burst2beat
# Write Buffer
w_buffer = stream.SyncFIFO(w_description(axi.data_width), buffer_depth, buffered=True)
w_buffer = stream.SyncFIFO(w_description(axi.data_width, axi.id_width),
buffer_depth, buffered=True)
self.submodules.w_buffer = w_buffer
# Write ID Buffer & Response
@ -172,7 +122,7 @@ class LiteDRAMAXI2NativeW(Module):
w_buffer.source.last &
w_buffer.source.ready,
resp_buffer.sink.valid.eq(1),
resp_buffer.sink.resp.eq(resp_types["okay"]),
resp_buffer.sink.resp.eq(RESP_OKAY),
resp_buffer.sink.id.eq(id_buffer.source.id),
id_buffer.source.ready.eq(1)
),
@ -200,7 +150,7 @@ class LiteDRAMAXI2NativeW(Module):
# Write Data
self.comb += [
w_buffer.source.connect(port.wdata, omit={"strb"}),
w_buffer.source.connect(port.wdata, omit={"strb", "id"}),
port.wdata.we.eq(w_buffer.source.strb)
]
@ -274,7 +224,7 @@ class LiteDRAMAXI2NativeR(Module):
self.comb += [
port.rdata.connect(r_buffer.sink, omit={"bank"}),
r_buffer.source.connect(axi.r, omit={"id", "last"}),
axi.r.resp.eq(resp_types["okay"])
axi.r.resp.eq(RESP_OKAY)
]

16
test/test_axi.py
View file

@ -12,7 +12,7 @@ from litex.gen.sim import *
class Burst:
def __init__(self, addr, type=burst_types["fixed"], len=0, size=0):
def __init__(self, addr, type=BURST_FIXED, len=0, size=0):
self.addr = addr
self.type = type
self.len = len
@ -21,10 +21,10 @@ class Burst:
def to_beats(self):
r = []
for i in range(self.len + 1):
if self.type == burst_types["incr"]:
if self.type == BURST_INCR:
offset = i*2**(self.size)
r += [Beat(self.addr + offset)]
elif self.type == burst_types["wrap"]:
elif self.type == BURST_WRAP:
offset = (i*2**(self.size))%((2**self.size)*(self.len))
r += [Beat(self.addr + offset)]
else:
@ -95,9 +95,9 @@ class TestAXI(unittest.TestCase):
prng = random.Random(42)
bursts = []
for i in range(32):
bursts.append(Burst(prng.randrange(2**32), burst_types["fixed"], prng.randrange(255), log2_int(32//8)))
bursts.append(Burst(prng.randrange(2**32), burst_types["incr"], prng.randrange(255), log2_int(32//8)))
bursts.append(Burst(4, burst_types["wrap"], 4-1, log2_int(2)))
bursts.append(Burst(prng.randrange(2**32), BURST_FIXED, prng.randrange(255), log2_int(32//8)))
bursts.append(Burst(prng.randrange(2**32), BURST_INCR, prng.randrange(255), log2_int(32//8)))
bursts.append(Burst(4, BURST_WRAP, 4-1, log2_int(2)))
# generate expexted dut output (beats for reference)
beats = []
@ -234,10 +234,10 @@ class TestAXI(unittest.TestCase):
_id = prng.randrange(2**8) if id_rand_enable else i
_len = prng.randrange(32) if len_rand_enable else i
_data = [prng.randrange(2**32) if data_rand_enable else j for j in range(_len + 1)]
writes.append(Write(offset, _data, _id, type=burst_types["incr"], len=_len, size=log2_int(32//8)))
writes.append(Write(offset, _data, _id, type=BURST_INCR, len=_len, size=log2_int(32//8)))
offset += _len + 1
# dummy reads to ensure datas have been written before the effective reads start.
dummy_reads = [Read(1023, [0], 0, type=burst_types["fixed"], len=0, size=log2_int(32//8)) for _ in range(32)]
dummy_reads = [Read(1023, [0], 0, type=BURST_FIXED, len=0, size=log2_int(32//8)) for _ in range(32)]
reads = dummy_reads + writes
# simulation