remove debug prints
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@ -158,13 +158,11 @@ class LiteDRAMCrossbar(Module):
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def split_master_addresses(self, bank_bits, rca_bits, cba_shift):
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def split_master_addresses(self, bank_bits, rca_bits, cba_shift):
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m_ba = [] # bank address
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m_ba = [] # bank address
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m_rca = [] # row and column address
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m_rca = [] # row and column address
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print("cba_shift: " + str(cba_shift))
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for master in self.masters:
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for master in self.masters:
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cba = Signal(self.bank_bits)
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cba = Signal(self.bank_bits)
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rca = Signal(self.rca_bits)
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rca = Signal(self.rca_bits)
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cba_upper = cba_shift + bank_bits
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cba_upper = cba_shift + bank_bits
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self.comb += cba.eq(master.cmd.adr[cba_shift:cba_upper])
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self.comb += cba.eq(master.cmd.adr[cba_shift:cba_upper])
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print("cba_shift: " + str(cba_shift) + " cba_upper: " + str(cba_upper))
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if cba_shift < self.rca_bits:
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if cba_shift < self.rca_bits:
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if cba_shift:
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if cba_shift:
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self.comb += rca.eq(Cat(master.cmd.adr[:cba_shift],
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self.comb += rca.eq(Cat(master.cmd.adr[:cba_shift],
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