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test: use @unittest.skip instead of commenting out code

This commit is contained in:
Jędrzej Boczar 2020-03-24 14:27:29 +01:00
parent 0afacba2ca
commit c39a6bd059
2 changed files with 39 additions and 37 deletions
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11
test/test_adaptation.py
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@ -196,11 +196,12 @@ class TestAdaptation(MemoryTestDataMixin, unittest.TestCase):
dut = ConverterDUT(user_data_width=32, native_data_width=256, mem_depth=len(data["expected"])) dut = ConverterDUT(user_data_width=32, native_data_width=256, mem_depth=len(data["expected"]))
self.converter_readback_test(dut, data["pattern"], data["expected"]) self.converter_readback_test(dut, data["pattern"], data["expected"])
# # TODO: implement case when user does not write all words (LiteDRAMNativeWritePortUpConverter) # TODO: implement case when user does not write all words (LiteDRAMNativeWritePortUpConverter)
# def test_converter_up_not_aligned(self): @unittest.skip("Only full-burst writes currently supported")
# data = self.pattern_test_data["8bit_to_32bit_not_aligned"] def test_converter_up_not_aligned(self):
# dut = ConverterDUT(user_data_width=8, native_data_width=32, mem_depth=len(data["expected"])) data = self.pattern_test_data["8bit_to_32bit_not_aligned"]
# self.converter_readback_test(dut, data["pattern"], data["expected"]) dut = ConverterDUT(user_data_width=8, native_data_width=32, mem_depth=len(data["expected"]))
self.converter_readback_test(dut, data["pattern"], data["expected"])
def cdc_readback_test(self, dut, pattern, mem_expected, clocks): def cdc_readback_test(self, dut, pattern, mem_expected, clocks):
assert len(set(adr for adr, _ in pattern)) == len(pattern), "Pattern has duplicates!" assert len(set(adr for adr, _ in pattern)) == len(pattern), "Pattern has duplicates!"

65
test/test_bist.py
View File

@ -390,35 +390,36 @@ class TestBIST(MemoryTestDataMixin, unittest.TestCase):
run_simulation(dut, generators) run_simulation(dut, generators)
# FIXME: synchronization between CSRs: `start` and `base`, `done` and `errors` # FIXME: synchronization between CSRs: `start` and `base`, `done` and `errors`
# def test_bist_csr_cdc(self): @unittest.skip("CSRs CDC synchronization problem (issue #167)")
# class DUT(Module): def test_bist_csr_cdc(self):
# def __init__(self): class DUT(Module):
# port_kwargs = dict(address_width=32, data_width=32, clock_domain="async") def __init__(self):
# self.write_port = LiteDRAMNativeWritePort(**port_kwargs) port_kwargs = dict(address_width=32, data_width=32, clock_domain="async")
# self.read_port = LiteDRAMNativeReadPort(**port_kwargs) self.write_port = LiteDRAMNativeWritePort(**port_kwargs)
# self.submodules.generator = LiteDRAMBISTGenerator(self.write_port) self.read_port = LiteDRAMNativeReadPort(**port_kwargs)
# self.submodules.checker = LiteDRAMBISTChecker(self.read_port) self.submodules.generator = LiteDRAMBISTGenerator(self.write_port)
# self.submodules.checker = LiteDRAMBISTChecker(self.read_port)
# def main_generator(dut, mem):
# generator = GenCheckCSRDriver(dut.generator) def main_generator(dut, mem):
# checker = GenCheckCSRDriver(dut.checker) generator = GenCheckCSRDriver(dut.generator)
# yield from self.bist_test(generator, checker, mem) checker = GenCheckCSRDriver(dut.checker)
# yield from self.bist_test(generator, checker, mem)
# # dut
# dut = DUT() # dut
# mem = DRAMMemory(32, 48) dut = DUT()
# mem = DRAMMemory(32, 48)
# generators = {
# "sys": [ generators = {
# main_generator(dut, mem), "sys": [
# ], main_generator(dut, mem),
# "async": [ ],
# mem.write_handler(dut.write_port), "async": [
# mem.read_handler(dut.read_port) mem.write_handler(dut.write_port),
# ] mem.read_handler(dut.read_port)
# } ]
# clocks = { }
# "sys": 10, clocks = {
# "async": (7, 3), "sys": 10,
# } "async": (7, 3),
# run_simulation(dut, generators, clocks) }
run_simulation(dut, generators, clocks)