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test: use @unittest.skip instead of commenting out code

This commit is contained in:
Jędrzej Boczar 2020-03-24 14:27:29 +01:00
parent 0afacba2ca
commit c39a6bd059
2 changed files with 39 additions and 37 deletions
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11
test/test_adaptation.py
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@ -196,11 +196,12 @@ class TestAdaptation(MemoryTestDataMixin, unittest.TestCase):
dut = ConverterDUT(user_data_width=32, native_data_width=256, mem_depth=len(data["expected"]))
self.converter_readback_test(dut, data["pattern"], data["expected"])
# # TODO: implement case when user does not write all words (LiteDRAMNativeWritePortUpConverter)
# def test_converter_up_not_aligned(self):
# data = self.pattern_test_data["8bit_to_32bit_not_aligned"]
# dut = ConverterDUT(user_data_width=8, native_data_width=32, mem_depth=len(data["expected"]))
# self.converter_readback_test(dut, data["pattern"], data["expected"])
# TODO: implement case when user does not write all words (LiteDRAMNativeWritePortUpConverter)
@unittest.skip("Only full-burst writes currently supported")
def test_converter_up_not_aligned(self):
data = self.pattern_test_data["8bit_to_32bit_not_aligned"]
dut = ConverterDUT(user_data_width=8, native_data_width=32, mem_depth=len(data["expected"]))
self.converter_readback_test(dut, data["pattern"], data["expected"])
def cdc_readback_test(self, dut, pattern, mem_expected, clocks):
assert len(set(adr for adr, _ in pattern)) == len(pattern), "Pattern has duplicates!"

65
test/test_bist.py
View File

@ -390,35 +390,36 @@ class TestBIST(MemoryTestDataMixin, unittest.TestCase):
run_simulation(dut, generators)
# FIXME: synchronization between CSRs: `start` and `base`, `done` and `errors`
# def test_bist_csr_cdc(self):
# class DUT(Module):
# def __init__(self):
# port_kwargs = dict(address_width=32, data_width=32, clock_domain="async")
# self.write_port = LiteDRAMNativeWritePort(**port_kwargs)
# self.read_port = LiteDRAMNativeReadPort(**port_kwargs)
# self.submodules.generator = LiteDRAMBISTGenerator(self.write_port)
# self.submodules.checker = LiteDRAMBISTChecker(self.read_port)
#
# def main_generator(dut, mem):
# generator = GenCheckCSRDriver(dut.generator)
# checker = GenCheckCSRDriver(dut.checker)
# yield from self.bist_test(generator, checker, mem)
#
# # dut
# dut = DUT()
# mem = DRAMMemory(32, 48)
#
# generators = {
# "sys": [
# main_generator(dut, mem),
# ],
# "async": [
# mem.write_handler(dut.write_port),
# mem.read_handler(dut.read_port)
# ]
# }
# clocks = {
# "sys": 10,
# "async": (7, 3),
# }
# run_simulation(dut, generators, clocks)
@unittest.skip("CSRs CDC synchronization problem (issue #167)")
def test_bist_csr_cdc(self):
class DUT(Module):
def __init__(self):
port_kwargs = dict(address_width=32, data_width=32, clock_domain="async")
self.write_port = LiteDRAMNativeWritePort(**port_kwargs)
self.read_port = LiteDRAMNativeReadPort(**port_kwargs)
self.submodules.generator = LiteDRAMBISTGenerator(self.write_port)
self.submodules.checker = LiteDRAMBISTChecker(self.read_port)
def main_generator(dut, mem):
generator = GenCheckCSRDriver(dut.generator)
checker = GenCheckCSRDriver(dut.checker)
yield from self.bist_test(generator, checker, mem)
# dut
dut = DUT()
mem = DRAMMemory(32, 48)
generators = {
"sys": [
main_generator(dut, mem),
],
"async": [
mem.write_handler(dut.write_port),
mem.read_handler(dut.read_port)
]
}
clocks = {
"sys": 10,
"async": (7, 3),
}
run_simulation(dut, generators, clocks)