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examples: update sim

This commit is contained in:
Florent Kermarrec 2019-03-15 20:16:42 +01:00
parent 201a0e2fb4
commit c4161cfbfe
1 changed files with 25 additions and 23 deletions
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48
examples/sim/sim_config.py
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@ -2,32 +2,34 @@ from litedram.modules import MT41K128M16
from litedram.phy import A7DDRPHY
core_config = {
# cpu
"cpu": None,
# General ------------------------------------------------------------------
"cpu": None, # Type of CPU used for init/calib (vexriscv, lm32)
"speedgrade": -1, # FPGA speedgrade
"memtype": "DDR3", # DRAM type
# modules / phy
"sdram_module": MT41K128M16,
"sdram_module_nb": 1,
"sdram_module_speedgrade": "800",
"sdram_rank_nb": 1,
"sdram_phy": A7DDRPHY,
# PHY ----------------------------------------------------------------------
"cmd_delay": 0, # Command additional delay (in taps)
"cmd_latency": 0, # Command additional latency
"sdram_module": MT41K128M16, # SDRAM modules of the board or SO-DIMM
"sdram_module_nb": 2, # Number of byte groups
"sdram_rank_nb": 1, # Number of ranks
"sdram_phy": A7DDRPHY, # Type of FPGA PHY
# electrical
"rtt_nom": "60ohm",
"rtt_wr": "60ohm",
"ron": "34ohm",
# Electrical ---------------------------------------------------------------
"rtt_nom": "60ohm", # Nominal termination
"rtt_wr": "60ohm", # Write termination
"ron": "34ohm", # Output driver impedance
# freqs
"input_clk_freq": 100e6,
"sys_clk_freq": 100e6,
"iodelay_clk_freq": 200e6,
# Frequency ----------------------------------------------------------------
"input_clk_freq": 100e6, # Input clock frequency
"sys_clk_freq": 100e6, # System clock frequency (DDR_clk = 4 x sys_clk)
"iodelay_clk_freq": 200e6, # IODELAYs reference clock frequency
# controller
"cmd_buffer_depth": 8,
"write_time": 16,
"read_time": 32,
# Core ---------------------------------------------------------------------
"cmd_buffer_depth": 16, # Depth of the command buffer
# user_ports
"user_ports_nb": 2,
"user_ports_type": "native"
# User Ports ---------------------------------------------------------------
"user_ports_nb": 2, # Number of user ports
"user_ports_type": "native", # Type of ports (axi, native)
}