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bench/targets: add optional analyzer on all test targets.

This commit is contained in:
Florent Kermarrec 2020-12-10 08:44:35 +01:00
parent 62845f1ec9
commit c472499131
5 changed files with 93 additions and 45 deletions
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29
bench/arty.py
View File

@ -61,7 +61,7 @@ class _CRG(Module, AutoCSR):
# Bench SoC ----------------------------------------------------------------------------------------
class BenchSoC(SoCCore):
def __init__(self, uart="crossover", sys_clk_freq=int(125e6), with_bist=False):
def __init__(self, uart="crossover", sys_clk_freq=int(125e6), with_bist=False, with_analyzer=False):
platform = arty.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -100,6 +100,16 @@ class BenchSoC(SoCCore):
self.add_csr("ethphy")
self.add_etherbone(phy=self.ethphy)
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
from litescope import LiteScopeAnalyzer
analyzer_signals = [self.ddrphy.dfi]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
depth = 256,
clock_domain = "sys",
csr_csv = "analyzer.csv")
self.add_csr("analyzer")
# Leds -------------------------------------------------------------------------------------
from litex.soc.cores.led import LedChaser
self.submodules.leds = LedChaser(
@ -111,16 +121,17 @@ class BenchSoC(SoCCore):
def main():
parser = argparse.ArgumentParser(description="LiteDRAM Bench on Arty A7")
parser.add_argument("--uart", default="crossover", help="Selected UART: crossover (default) or serial")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--with-bist", action="store_true", help="Add BIST Generator/Checker")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--load-bios", action="store_true", help="Load BIOS")
parser.add_argument("--set-sys-clk", default=None, help="Set sys_clk")
parser.add_argument("--test", action="store_true", help="Run Full Bench")
parser.add_argument("--uart", default="crossover", help="Selected UART: crossover (default) or serial")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--with-bist", action="store_true", help="Add BIST Generator/Checker")
parser.add_argument("--with-analyzer", action="store_true", help="Add Analyzer")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--load-bios", action="store_true", help="Load BIOS")
parser.add_argument("--set-sys-clk", default=None, help="Set sys_clk")
parser.add_argument("--test", action="store_true", help="Run Full Bench")
args = parser.parse_args()
soc = BenchSoC(uart=args.uart, with_bist=args.with_bist)
soc = BenchSoC(uart=args.uart, with_bist=args.with_bist, with_analyzer=args.with_analyzer)
builder = Builder(soc, csr_csv="csr.csv")
builder.build(run=args.build)

34
bench/genesys2.py
View File

@ -59,7 +59,7 @@ class _CRG(Module, AutoCSR):
# Bench SoC ----------------------------------------------------------------------------------------
class BenchSoC(SoCCore):
def __init__(self, uart="crossover", sys_clk_freq=int(125e6), with_bist=False):
def __init__(self, uart="crossover", sys_clk_freq=int(125e6), with_bist=False, with_analyzer=False):
platform = genesys2.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -99,13 +99,14 @@ class BenchSoC(SoCCore):
self.add_etherbone(phy=self.ethphy)
# Analyzer ---------------------------------------------------------------------------------
from litescope import LiteScopeAnalyzer
analyzer_signals = [self.ddrphy.dfi]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
depth = 512,
clock_domain = "sys",
csr_csv = "analyzer.csv")
self.add_csr("analyzer")
if with_analyzer:
from litescope import LiteScopeAnalyzer
analyzer_signals = [self.ddrphy.dfi]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
depth = 512,
clock_domain = "sys",
csr_csv = "analyzer.csv")
self.add_csr("analyzer")
# Leds -------------------------------------------------------------------------------------
from litex.soc.cores.led import LedChaser
@ -118,16 +119,17 @@ class BenchSoC(SoCCore):
def main():
parser = argparse.ArgumentParser(description="LiteDRAM Bench on Genesys2")
parser.add_argument("--uart", default="crossover", help="Selected UART: crossover (default) or serial")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--with-bist", action="store_true", help="Add BIST Generator/Checker")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--load-bios", action="store_true", help="Load BIOS")
parser.add_argument("--set-sys-clk", default=None, help="Set sys_clk")
parser.add_argument("--test", action="store_true", help="Run Full Bench")
parser.add_argument("--uart", default="crossover", help="Selected UART: crossover (default) or serial")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--with-bist", action="store_true", help="Add BIST Generator/Checker")
parser.add_argument("--with-analyzer", action="store_true", help="Add Analyzer")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--load-bios", action="store_true", help="Load BIOS")
parser.add_argument("--set-sys-clk", default=None, help="Set sys_clk")
parser.add_argument("--test", action="store_true", help="Run Full Bench")
args = parser.parse_args()
soc = BenchSoC(uart=args.uart, with_bist=args.with_bist)
soc = BenchSoC(uart=args.uart, with_bist=args.with_bist, with_analyzer=args.with_analyzer)
builder = Builder(soc, csr_csv="csr.csv")
builder.build(run=args.build)

29
bench/kc705.py
View File

@ -59,7 +59,7 @@ class _CRG(Module, AutoCSR):
# Bench SoC ----------------------------------------------------------------------------------------
class BenchSoC(SoCCore):
def __init__(self, uart="crossover", sys_clk_freq=int(125e6), with_bist=False):
def __init__(self, uart="crossover", sys_clk_freq=int(125e6), with_bist=False, with_analyzer=False):
platform = kc705.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -98,6 +98,16 @@ class BenchSoC(SoCCore):
self.add_csr("ethphy")
self.add_etherbone(phy=self.ethphy)
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
from litescope import LiteScopeAnalyzer
analyzer_signals = [self.ddrphy.dfi]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
depth = 256,
clock_domain = "sys",
csr_csv = "analyzer.csv")
self.add_csr("analyzer")
# Leds -------------------------------------------------------------------------------------
from litex.soc.cores.led import LedChaser
self.submodules.leds = LedChaser(
@ -109,16 +119,17 @@ class BenchSoC(SoCCore):
def main():
parser = argparse.ArgumentParser(description="LiteDRAM Bench on KC705")
parser.add_argument("--uart", default="crossover", help="Selected UART: crossover (default) or serial")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--with-bist", action="store_true", help="Add BIST Generator/Checker")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--load-bios", action="store_true", help="Load BIOS")
parser.add_argument("--set-sys-clk", default=None, help="Set sys_clk")
parser.add_argument("--test", action="store_true", help="Run Full Bench")
parser.add_argument("--uart", default="crossover", help="Selected UART: crossover (default) or serial")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--with-bist", action="store_true", help="Add BIST Generator/Checker")
parser.add_argument("--with-analyzer", action="store_true", help="Add Analyzer")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--load-bios", action="store_true", help="Load BIOS")
parser.add_argument("--set-sys-clk", default=None, help="Set sys_clk")
parser.add_argument("--test", action="store_true", help="Run Full Bench")
args = parser.parse_args()
soc = BenchSoC(uart=args.uart, with_bist=args.with_bist)
soc = BenchSoC(uart=args.uart, with_bist=args.with_bist, with_analyzer=args.with_analyzer)
builder = Builder(soc, csr_csv="csr.csv")
builder.build(run=args.build)

30
bench/kcu105.py
View File

@ -10,6 +10,7 @@ import os
import argparse
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.boards.platforms import kcu105
@ -77,7 +78,7 @@ class _CRG(Module, AutoCSR):
# Bench SoC ----------------------------------------------------------------------------------------
class BenchSoC(SoCCore):
def __init__(self, uart="crossover", sys_clk_freq=int(125e6), with_bist=False):
def __init__(self, uart="crossover", sys_clk_freq=int(125e6), with_bist=False, with_analyzer=False):
platform = kcu105.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -118,6 +119,16 @@ class BenchSoC(SoCCore):
self.platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]")
self.add_etherbone(phy=self.ethphy)
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
from litescope import LiteScopeAnalyzer
analyzer_signals = [self.ddrphy.dfi]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
depth = 256,
clock_domain = "sys",
csr_csv = "analyzer.csv")
self.add_csr("analyzer")
# Leds -------------------------------------------------------------------------------------
from litex.soc.cores.led import LedChaser
self.submodules.leds = LedChaser(
@ -129,16 +140,17 @@ class BenchSoC(SoCCore):
def main():
parser = argparse.ArgumentParser(description="LiteDRAM Bench on KCU105")
parser.add_argument("--uart", default="crossover", help="Selected UART: crossover (default) or serial")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--with-bist", action="store_true", help="Add BIST Generator/Checker")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--load-bios", action="store_true", help="Load BIOS")
parser.add_argument("--set-sys-clk", default=None, help="Set sys_clk")
parser.add_argument("--test", action="store_true", help="Run Full Bench")
parser.add_argument("--uart", default="crossover", help="Selected UART: crossover (default) or serial")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--with-bist", action="store_true", help="Add BIST Generator/Checker")
parser.add_argument("--with-analyzer", action="store_true", help="Add Analyzer")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--load-bios", action="store_true", help="Load BIOS")
parser.add_argument("--set-sys-clk", default=None, help="Set sys_clk")
parser.add_argument("--test", action="store_true", help="Run Full Bench")
args = parser.parse_args()
soc = BenchSoC(uart=args.uart, with_bist=args.with_bist)
soc = BenchSoC(uart=args.uart, with_bist=args.with_bist, with_analyzer=args.with_analyzer)
builder = Builder(soc, csr_csv="csr.csv")
builder.build(run=args.build)

16
bench/xcu1525.py
View File

@ -10,6 +10,7 @@ import os
import argparse
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import xcu1525
@ -73,7 +74,7 @@ class _CRG(Module, AutoCSR):
# Bench SoC ----------------------------------------------------------------------------------------
class BenchSoC(SoCCore):
def __init__(self, uart="crossover", sys_clk_freq=int(125e6), channel=0, with_bist=False):
def __init__(self, uart="crossover", sys_clk_freq=int(125e6), channel=0, with_bist=False, with_analyzer=False):
platform = xcu1525.Platform()
# SoCCore ----------------------------------------------------------------------------------
@ -107,6 +108,16 @@ class BenchSoC(SoCCore):
if uart != "serial":
self.add_uartbone(name="serial", clk_freq=100e6, baudrate=115200, cd="uart")
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
from litescope import LiteScopeAnalyzer
analyzer_signals = [self.ddrphy.dfi]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
depth = 256,
clock_domain = "sys",
csr_csv = "analyzer.csv")
self.add_csr("analyzer")
# Leds -------------------------------------------------------------------------------------
from litex.soc.cores.led import LedChaser
self.submodules.leds = LedChaser(
@ -122,13 +133,14 @@ def main():
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--channel", default="0", help="DDRAM channel 0 (default), 1, 2 or 3")
parser.add_argument("--with-bist", action="store_true", help="Add BIST Generator/Checker")
parser.add_argument("--with-analyzer", action="store_true", help="Add Analyzer")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--load-bios", action="store_true", help="Load BIOS")
parser.add_argument("--set-sys-clk", default=None, help="Set sys_clk")
parser.add_argument("--test", action="store_true", help="Run Full Bench")
args = parser.parse_args()
soc = BenchSoC(uart=args.uart, channel=int(args.channel, 0), with_bist=args.with_bist)
soc = BenchSoC(uart=args.uart, channel=int(args.channel, 0), with_bist=args.with_bist, with_analyzer=args.with_analyzer)
builder = Builder(soc, output_dir="build/xcu1525_ch{}".format(args.channel), csr_csv="csr.csv")
builder.build(run=args.build)