test/reference: update.
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@ -51,11 +51,11 @@ __attribute__((unused)) static void command_p3(int cmd)
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}
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#define sdram_dfii_pird_address_write(X) sdram_dfii_pi1_address_write(X)
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#define sdram_dfii_pird_address_write(X) sdram_dfii_pi3_address_write(X)
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#define sdram_dfii_piwr_address_write(X) sdram_dfii_pi2_address_write(X)
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#define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi1_baddress_write(X)
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#define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi3_baddress_write(X)
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#define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi2_baddress_write(X)
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#define command_prd(X) command_p1(X)
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#define command_prd(X) command_p3(X)
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#define command_pwr(X) command_p2(X)
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#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE
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@ -120,8 +120,8 @@ static void init_sequence(void)
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sdram_dfii_pi0_baddress_write(1);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
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/* Load Mode Register 0, CL=11, BL=8 */
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sdram_dfii_pi0_address_write(0x110);
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/* Load Mode Register 0, CL=9, BL=8 */
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sdram_dfii_pi0_address_write(0x100);
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sdram_dfii_pi0_baddress_write(0);
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command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
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cdelay(200);
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@ -21,6 +21,6 @@ init_sequence = [
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("Load Mode Register 4", 0, 4, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0),
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("Load Mode Register 2, CWL=9", 512, 2, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0),
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("Load Mode Register 1", 769, 1, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0),
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("Load Mode Register 0, CL=11, BL=8", 272, 0, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 200),
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("Load Mode Register 0, CL=9, BL=8", 256, 0, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 200),
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("ZQ Calibration", 1024, 0, dfii_command_we|dfii_command_cs, 200),
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]
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