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test/reference: update.

This commit is contained in:
Florent Kermarrec 2020-09-30 11:51:24 +02:00
parent d06e2dda23
commit c4d7083677
2 changed files with 6 additions and 6 deletions
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10
test/reference/ddr4_init.h
View File

@ -51,11 +51,11 @@ __attribute__((unused)) static void command_p3(int cmd)
} }
#define sdram_dfii_pird_address_write(X) sdram_dfii_pi1_address_write(X) #define sdram_dfii_pird_address_write(X) sdram_dfii_pi3_address_write(X)
#define sdram_dfii_piwr_address_write(X) sdram_dfii_pi2_address_write(X) #define sdram_dfii_piwr_address_write(X) sdram_dfii_pi2_address_write(X)
#define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi1_baddress_write(X) #define sdram_dfii_pird_baddress_write(X) sdram_dfii_pi3_baddress_write(X)
#define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi2_baddress_write(X) #define sdram_dfii_piwr_baddress_write(X) sdram_dfii_pi2_baddress_write(X)
#define command_prd(X) command_p1(X) #define command_prd(X) command_p3(X)
#define command_pwr(X) command_p2(X) #define command_pwr(X) command_p2(X)
#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE #define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE
@ -120,8 +120,8 @@ static void init_sequence(void)
sdram_dfii_pi0_baddress_write(1); sdram_dfii_pi0_baddress_write(1);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
/* Load Mode Register 0, CL=11, BL=8 */ /* Load Mode Register 0, CL=9, BL=8 */
sdram_dfii_pi0_address_write(0x110); sdram_dfii_pi0_address_write(0x100);
sdram_dfii_pi0_baddress_write(0); sdram_dfii_pi0_baddress_write(0);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS); command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
cdelay(200); cdelay(200);

2
test/reference/ddr4_init.py
View File

@ -21,6 +21,6 @@ init_sequence = [
("Load Mode Register 4", 0, 4, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0), ("Load Mode Register 4", 0, 4, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0),
("Load Mode Register 2, CWL=9", 512, 2, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0), ("Load Mode Register 2, CWL=9", 512, 2, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0),
("Load Mode Register 1", 769, 1, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0), ("Load Mode Register 1", 769, 1, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 0),
("Load Mode Register 0, CL=11, BL=8", 272, 0, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 200), ("Load Mode Register 0, CL=9, BL=8", 256, 0, dfii_command_ras|dfii_command_cas|dfii_command_we|dfii_command_cs, 200),
("ZQ Calibration", 1024, 0, dfii_command_we|dfii_command_cs, 200), ("ZQ Calibration", 1024, 0, dfii_command_we|dfii_command_cs, 200),
] ]