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test/test_bist: enable test_bist_csr_cdc (now passing with refactored CDC).

This commit is contained in:
Florent Kermarrec 2020-04-14 18:14:05 +02:00
parent 92e34d4d37
commit c55136c17a
1 changed files with 5 additions and 7 deletions
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12
test/test_bist.py
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@ -308,23 +308,23 @@ class TestBIST(MemoryTestDataMixin, unittest.TestCase):
def bist_test(self, generator, checker, mem):
# write
yield from generator.reset()
yield from generator.configure(16, 64)
yield from generator.configure(base=16, length=64)
yield from generator.run()
# Read (no errors)
yield from checker.reset()
yield from checker.configure(16, 64)
yield from checker.configure(base=16, length=64)
yield from checker.run()
self.assertEqual(checker.errors, 0)
# Corrupt memory (using generator)
yield from generator.reset()
yield from generator.configure(16 + 48, 64)
yield from generator.configure(base=16 + 48, length=64)
yield from generator.run()
# Read (errors)
yield from checker.reset()
yield from checker.configure(16, 64)
yield from checker.configure(base=16, length=64)
yield from checker.run()
# Errors for words:
# from (16 + 48) / 4 = 16 (corrupting generator start)
@ -333,7 +333,7 @@ class TestBIST(MemoryTestDataMixin, unittest.TestCase):
# Read (no errors)
yield from checker.reset()
yield from checker.configure(16 + 48, 64)
yield from checker.configure(base=16 + 48, length=64)
yield from checker.run()
self.assertEqual(checker.errors, 0)
@ -387,8 +387,6 @@ class TestBIST(MemoryTestDataMixin, unittest.TestCase):
]
run_simulation(dut, generators)
# FIXME: synchronization between CSRs: `start` and `base`, `done` and `errors`
@unittest.skip("CSRs CDC synchronization problem (issue #167)")
def test_bist_csr_cdc(self):
class DUT(Module):
def __init__(self):