test/test_bist: simplify and test modules directly not through CSR
This commit is contained in:
Florent Kermarrec
parent
e7fe539c73
commit
c56f90e865
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@ -1,28 +1,6 @@
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from litex.gen import *
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def toggle_re(reg):
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resig = reg.re
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# Check that reset isn't set
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reval = yield resig
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assert not reval, reval
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yield resig.eq(1)
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yield
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yield resig.eq(0)
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def reset_bist_module(module):
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# Toggle the reset
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yield from toggle_re(module.reset)
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# Takes a few clock cycles for the reset to have an effect
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for i in range(16):
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yield
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# Check some initial conditions are correct after reset.
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done = yield module.done.status
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assert not done, done
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def seed_to_data(seed, random=True, nbits=32):
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if nbits == 32:
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if random:
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@ -6,9 +6,8 @@ from litex.gen import *
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from litex.soc.interconnect.stream import *
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from litedram.common import LiteDRAMWritePort, LiteDRAMReadPort
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from litedram.frontend.bist import LiteDRAMBISTGenerator
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from litedram.frontend.bist import LiteDRAMBISTChecker
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from litedram.frontend.bist import LiteDRAMBISTCheckerScope
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from litedram.frontend.bist import _LiteDRAMBISTGenerator
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from litedram.frontend.bist import _LiteDRAMBISTChecker
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from test.common import *
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@ -17,157 +16,109 @@ class DUT(Module):
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def __init__(self):
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self.write_port = LiteDRAMWritePort(aw=32, dw=32)
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self.read_port = LiteDRAMReadPort(aw=32, dw=32)
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self.submodules.generator = LiteDRAMBISTGenerator(self.write_port, True)
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self.submodules.checker = LiteDRAMBISTChecker(self.read_port, True)
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self.submodules.checker_scope = LiteDRAMBISTCheckerScope(self.checker)
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self.submodules.generator = _LiteDRAMBISTGenerator(self.write_port, False)
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self.submodules.checker = _LiteDRAMBISTChecker(self.read_port, False)
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def main_generator(dut, mem):
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# Populate memory with random data
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random.seed(0)
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for i in range(0, len(mem.mem)):
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mem.mem[i] = random.randint(0, 2**mem.width)
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# write
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yield from reset_bist_module(dut.generator)
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yield dut.generator.base.storage.eq(16)
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yield dut.generator.length.storage.eq(64)
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for i in range(8):
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yield
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yield dut.generator.start.re.eq(1)
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yield dut.generator.reset.eq(1)
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yield
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yield dut.generator.start.re.eq(0)
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yield dut.generator.reset.eq(0)
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yield
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yield dut.generator.base.eq(16)
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yield dut.generator.length.eq(64)
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for i in range(8):
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yield
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while((yield dut.generator.done.status) == 0):
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yield dut.generator.start.eq(1)
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yield
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yield dut.generator.start.eq(0)
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for i in range(8):
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yield
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done = yield dut.generator.done.status
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while((yield dut.generator.done) == 0):
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yield
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done = yield dut.generator.done
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assert done, done
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# read with no errors
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yield from reset_bist_module(dut.checker)
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errors = yield dut.checker.err_count.status
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assert errors == 0, errors
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# read (no errors)
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yield dut.checker.reset.eq(1)
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yield
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yield dut.checker.reset.eq(0)
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yield
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yield dut.checker.base.storage.eq(16)
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yield dut.checker.length.storage.eq(64)
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yield dut.checker.base.eq(16)
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yield dut.checker.length.eq(64)
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for i in range(8):
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yield
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yield from toggle_re(dut.checker.start)
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for i in range(8):
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yield
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while((yield dut.checker.done.status) == 0):
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yield
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done = yield dut.checker.done.status
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yield dut.checker.start.eq(1)
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yield
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yield dut.checker.start.eq(0)
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yield
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while True:
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done = (yield dut.checker.done)
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if not done:
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yield
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else:
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break
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assert done, done
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errors = yield dut.checker.err_count.status
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errors = yield dut.checker.err_count
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assert errors == 0, errors
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# corrupt memory (4 errors)
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for i in range(4):
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mem.mem[i+16] = ~mem.mem[i+16]
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# read (4 errors)
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yield dut.checker.reset.eq(1)
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yield
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yield dut.checker.reset.eq(0)
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yield
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# read with one error
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yield from reset_bist_module(dut.checker)
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errors = yield dut.checker.err_count.status
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assert errors == 0, errors
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print("mem.mem[20]", hex(mem.mem[20]))
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assert mem.mem[20] == 0xffff000f, hex(mem.mem[20])
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mem.mem[20] = 0x200 # Make position 20 an error
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yield dut.checker.base.storage.eq(16)
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yield dut.checker.length.storage.eq(64)
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for i in range(8):
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yield
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yield from toggle_re(dut.checker.start)
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for i in range(8):
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yield
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while((yield dut.checker.done.status) == 0):
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yield
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done = yield dut.checker.done.status
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yield dut.checker.base.eq(16)
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yield dut.checker.length.eq(64)
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yield dut.checker.start.eq(1)
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yield
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yield dut.checker.start.eq(0)
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yield
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while True:
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done = (yield dut.checker.done)
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if not done:
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yield
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else:
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break
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assert done, done
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errors = yield dut.checker.err_count.status
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assert errors == 1, errors
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errors = yield dut.checker.err_count
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assert errors == 4, errors
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# revert memory
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for i in range(4):
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mem.mem[i+16] = ~mem.mem[i+16]
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# read (no errors)
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yield dut.checker.reset.eq(1)
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yield
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yield dut.checker.reset.eq(0)
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yield
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# read with two errors
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yield from reset_bist_module(dut.checker)
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errors = yield dut.checker.err_count.status
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assert errors == 0, errors
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print("mem.mem[21]", hex(mem.mem[21]))
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assert mem.mem[21] == 0xfff1ff1f, hex(mem.mem[21])
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mem.mem[21] = 0x210 # Make position 21 an error
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yield dut.checker.base.storage.eq(16)
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yield dut.checker.length.storage.eq(64)
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yield dut.checker.base.eq(16)
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yield dut.checker.length.eq(64)
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for i in range(8):
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yield
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yield from toggle_re(dut.checker.start)
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for i in range(8):
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yield
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while((yield dut.checker.done.status) == 0):
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yield
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done = yield dut.checker.done.status
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yield dut.checker.start.eq(1)
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yield
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yield dut.checker.start.eq(0)
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yield
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while True:
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done = (yield dut.checker.done)
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if not done:
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yield
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else:
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break
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assert done, done
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errors = yield dut.checker.err_count.status
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assert errors == 2, errors
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yield
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yield
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# check the scoped signals
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yield from reset_bist_module(dut.checker)
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errors = yield dut.checker.err_count.status
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errors = yield dut.checker.err_count
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assert errors == 0, errors
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yield dut.checker.base.storage.eq(16)
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yield dut.checker.length.storage.eq(64)
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for i in range(8):
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yield
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yield from toggle_re(dut.checker.start)
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for i in range(8):
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yield
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while((yield dut.checker_scope.data_error) == 0):
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yield
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err_addr = yield dut.checker_scope.data_address
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assert err_addr == 20, err_addr
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err_expect = yield dut.checker_scope.data_expected
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assert err_expect == 0xffff000f, hex(err_expect)
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err_actual = yield dut.checker_scope.data_actual
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assert err_actual == 0x200, err_actual
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yield
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errors = yield dut.checker.core.err_count
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assert errors == 1, errors
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while((yield dut.checker_scope.data_error) == 0):
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yield
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err_addr = yield dut.checker_scope.data_address
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assert err_addr == 21, err_addr
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err_expect = yield dut.checker_scope.data_expected
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assert err_expect == 0xfff1ff1f, hex(err_expect)
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err_actual = yield dut.checker_scope.data_actual
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assert err_actual == 0x210, hex(err_actual)
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yield
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errors = yield dut.checker.core.err_count
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assert errors == 2, errors
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while((yield dut.checker.done.status) == 0):
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yield
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done = yield dut.checker.done.status
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assert done, done
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errors = yield dut.checker.err_count.status
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assert errors == 2, errors
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yield
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yield
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class TestBIST(unittest.TestCase):
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def test(self):
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