frontend/ecc: Reduce write byte enable granularity from DRAM's full burst data-width to DRAM's data-width.
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@ -16,7 +16,7 @@ Features:
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- Errors reporting.
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Limitations:
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- Byte enable not supported for writes.
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- Write byte enable granularity of DRAM's data-width.
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"""
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from migen import *
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@ -37,15 +37,27 @@ class LiteDRAMNativePortECCW(Module):
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# # #
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# Control (ECC encoding is combinatorial).
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self.comb += sink.connect(source, omit={"data", "we"}),
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# Data Path.
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for i in range(8):
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encoder = ECCEncoder(data_width_from//8)
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self.submodules += encoder
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ecc_width_from = data_width_from//8
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ecc_width_to = data_width_to//8
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# Encoder.
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self.submodules.encoder = encoder = ECCEncoder(ecc_width_from)
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self.comb += [
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sink.connect(source, omit={"data", "we"}),
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encoder.i.eq(sink.data[i*data_width_from//8:(i+1)*data_width_from//8]),
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source.data[i*data_width_to//8:(i+1)*data_width_to//8].eq(encoder.o)
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# Input.
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encoder.i.eq(sink.data[i*ecc_width_from:(i+1)*ecc_width_from]),
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# Output.
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# We always have to store the full ECC-Word so byte enable is not supported within
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# an ECC word. If any of the byte enable is set, the full ECC-Word is written.
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If(sink.we[i*ecc_width_from//8:(i+1)*ecc_width_from//8] != 0,
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source.we[i*ecc_width_to//8:(i+1)*ecc_width_to//8].eq(2**ecc_width_to-1)
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),
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source.data[i*ecc_width_to:(i+1)*ecc_width_to].eq(encoder.o)
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]
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self.comb += If(sink.we != 0, source.we.eq(2**len(source.we)-1))
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# LiteDRAMNativePortECCR ---------------------------------------------------------------------------
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@ -59,15 +71,24 @@ class LiteDRAMNativePortECCR(Module):
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# # #
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# Control Path (ECC encoding is combinatorial).
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self.comb += sink.connect(source, omit={"data"})
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# Data Path.
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for i in range(8):
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decoder = ECCDecoder(data_width_from//8)
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self.submodules += decoder
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ecc_width_to = data_width_to//8
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ecc_width_from = data_width_from//8
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# Decoder.
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self.submodules.decoder = decoder = ECCDecoder(ecc_width_from)
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self.comb += [
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# Enable.
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decoder.enable.eq(self.enable),
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decoder.i.eq(sink.data[i*data_width_to//8:(i+1)*data_width_to//8]),
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source.data[i*data_width_from//8:(i+1)*data_width_from//8].eq(decoder.o),
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# Input.
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decoder.i.eq(sink.data[i*ecc_width_to:(i+1)*ecc_width_to]),
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# Output.
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source.data[i*ecc_width_from:(i+1)*ecc_width_from].eq(decoder.o),
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# Bitflip/Error reporting.
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If(source.valid,
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self.sec[i].eq(decoder.sec),
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self.ded[i].eq(decoder.ded)
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@ -95,7 +116,7 @@ class LiteDRAMNativePortECC(Module, AutoCSR):
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# Cmd --------------------------------------------------------------------------------------
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self.comb += port_from.cmd.connect(port_to.cmd)
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# Wdata (ecc encoding) ---------------------------------------------------------------------
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# Wdata (ECC) encoding) --------------------------------------------------------------------
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ecc_wdata = LiteDRAMNativePortECCW(port_from.data_width, port_to.data_width)
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ecc_wdata = BufferizeEndpoints({"source": DIR_SOURCE})(ecc_wdata)
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self.submodules += ecc_wdata
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@ -106,7 +127,7 @@ class LiteDRAMNativePortECC(Module, AutoCSR):
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if with_error_injection:
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self.comb += port_to.wdata.data[:8].eq(self.flip.storage ^ ecc_wdata.source.data[:8])
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# Rdata (ecc decoding) ---------------------------------------------------------------------
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# Rdata (ECC decoding) ---------------------------------------------------------------------
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sec = Signal()
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ded = Signal()
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ecc_rdata = LiteDRAMNativePortECCR(port_from.data_width, port_to.data_width)
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