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phy/ecp5ddrphy: simplify ECP5DDRPHYInit, integrate it in the PHY, add burstdet registers
This commit is contained in:
Florent Kermarrec
parent
4274db809e
commit
c65ff974b6
1 changed files with 80 additions and 113 deletions
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@ -5,7 +5,7 @@ import math
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from collections import OrderedDict
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from migen import *
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from migen.genlib.misc import BitSlip
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from migen.genlib.misc import timeline, BitSlip
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from migen.fhdl.specials import Tristate
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from migen.genlib.cdc import MultiReg
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from migen.genlib.misc import WaitTimer
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@ -36,118 +36,78 @@ def get_sys_phases(nphases, sys_latency, cas_latency):
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cmd_phase = (dat_phase - 1)%nphases
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return cmd_phase, dat_phase
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# Lattice ECP5 DDR PHY -----------------------------------------------------------------------------
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# Lattice ECP5 DDR PHY Initialization --------------------------------------------------------------
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class ECP5DDRPHYInit(Module):
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def __init__(self, crg, phy):
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dll_lock = Signal()
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dll_lock_sync = Signal()
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uddcntl = Signal(reset=0b0)
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stop = Signal()
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def __init__(self, eclk_cd):
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self.pause = Signal()
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self.stop = Signal()
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self.delay = Signal()
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freeze = Signal()
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pause = Signal()
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ddr_rst = Signal()
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# # #
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# Synchronise DDRDLL lock
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self.specials += MultiReg(dll_lock, dll_lock_sync, "init")
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# Reset & startup FSM
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init_timer = ClockDomainsRenamer("init")(WaitTimer(5))
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self.submodules += init_timer
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reset_ddr_done = Signal()
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uddcntl_done = Signal()
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fsm = ClockDomainsRenamer("init")(FSM(reset_state="WAIT_LOCK"))
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self.submodules += fsm
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fsm.act("WAIT_LOCK",
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If(dll_lock_sync,
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init_timer.wait.eq(1),
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If(init_timer.done,
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init_timer.wait.eq(0),
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If(uddcntl_done,
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NextState("READY")
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).Elif(reset_ddr_done,
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NextState("PAUSE")
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).Else(
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NextState("FREEZE")
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)
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)
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)
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)
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fsm.act("FREEZE",
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freeze.eq(1),
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init_timer.wait.eq(1),
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If(init_timer.done,
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init_timer.wait.eq(0),
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If(reset_ddr_done,
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NextState("WAIT_LOCK")
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).Else(
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NextState("STOP")
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)
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)
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)
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fsm.act("STOP",
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stop.eq(1),
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freeze.eq(1),
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init_timer.wait.eq(1),
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If(init_timer.done,
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init_timer.wait.eq(0),
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If(reset_ddr_done,
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NextState("FREEZE")
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).Else(
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NextState("RESET_DDR")
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)
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)
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)
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fsm.act("RESET_DDR",
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stop.eq(1),
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freeze.eq(1),
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ddr_rst.eq(1),
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init_timer.wait.eq(1),
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If(init_timer.done,
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init_timer.wait.eq(0),
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NextValue(reset_ddr_done, 1),
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NextState("STOP")
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)
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)
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fsm.act("PAUSE",
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pause.eq(1),
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init_timer.wait.eq(1),
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If(init_timer.done,
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init_timer.wait.eq(0),
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If(uddcntl_done,
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NextState("WAIT_LOCK")
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).Else(
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NextState("UDDCNTL")
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)
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)
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)
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fsm.act("UDDCNTL",
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uddcntl.eq(1),
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pause.eq(1),
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init_timer.wait.eq(1),
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If(init_timer.done,
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init_timer.wait.eq(0),
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NextValue(uddcntl_done, 1),
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NextState("PAUSE")
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)
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)
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fsm.act("READY")
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self.comb += phy.pause.eq(pause)
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self.comb += crg.stop.eq(stop)
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new_lock = Signal()
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update = Signal()
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stop = Signal()
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freeze = Signal()
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pause = Signal()
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reset = Signal()
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# DDRDLLA instance -------------------------------------------------------------------------
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_lock = Signal()
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delay = Signal()
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self.specials += Instance("DDRDLLA",
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i_CLK=ClockSignal("sys2x"), # CHECKME
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i_RST=ResetSignal("init"), # CHECKME
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i_UDDCNTLN=~uddcntl,
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i_CLK=ClockSignal("sys2x"),
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i_RST=ResetSignal(),
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i_UDDCNTLN=~update,
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i_FREEZE=freeze,
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o_DDRDEL=phy.ddrdel,
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o_LOCK=dll_lock
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o_DDRDEL=delay,
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o_LOCK=_lock
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)
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self.sync.init += ResetSignal("sys2x").eq(ddr_rst) # CHECKME
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lock = Signal()
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lock_d = Signal()
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self.specials += MultiReg(_lock, lock)
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self.sync += lock_d.eq(lock)
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self.comb += new_lock.eq(lock & ~lock_d)
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# DDRDLLA/DDQBUFM/ECLK initialization sequence ---------------------------------------------
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t = 8 # in cycles
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self.sync.init += [
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# Wait DDRDLLA Lock
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timeline(new_lock, [
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# Freeze DDRDLLA
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(1*t, [freeze.eq(1)]),
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# Stop ECLK domain
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(2*t, [stop.eq(1)]),
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# Reset ECLK domain
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(3*t, [reset.eq(1)]),
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# Release ECLK domain reset
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(4*t, [reset.eq(0)]),
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# Release ECLK domain stop
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(5*t, [stop.eq(0)]),
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# Release DDRDLLA freeze
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(6*t, [freeze.eq(0)]),
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# Pause DQSBUFM
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(7*t, [pause.eq(1)]),
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# Update DDRDLLA
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(8*t, [update.eq(1)]),
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# Release DDRDMMA update
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(9*t, [update.eq(0)]),
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# Release DQSBUFM pause
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(10*t, [pause.eq(0)]),
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# Ready
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])
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]
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# ------------------------------------------------------------------------------------------
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self.comb += [
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self.pause.eq(pause),
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self.stop.eq(stop),
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self.delay.eq(delay),
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ResetSignal(eclk_cd).eq(reset)
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]
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# Lattice ECP5 DDR PHY -----------------------------------------------------------------------------
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class ECP5DDRPHY(Module, AutoCSR):
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def __init__(self, pads, sys_clk_freq=100e6):
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@ -160,8 +120,7 @@ class ECP5DDRPHY(Module, AutoCSR):
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nphases = 2
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# Init -------------------------------------------------------------------------------------
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self.pause = Signal()
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self.ddrdel = Signal()
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self.submodules.init = ClockDomainsRenamer("init")(ECP5DDRPHYInit("sys2x"))
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# Registers --------------------------------------------------------------------------------
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self._dly_sel = CSRStorage(databits//8)
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@ -171,9 +130,11 @@ class ECP5DDRPHY(Module, AutoCSR):
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self._rdly_dq_bitslip_rst = CSR()
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self._rdly_dq_bitslip = CSR()
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self._burstdet_clr = CSR()
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self._burstdet_seen = CSRStatus(databits//8)
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# Observation
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self.datavalid = Signal(databits//8)
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self.burstdet = Signal(databits//8)
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# PHY settings -----------------------------------------------------------------------------
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cl, cwl = get_cl_cw(memtype, tck)
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@ -200,9 +161,6 @@ class ECP5DDRPHY(Module, AutoCSR):
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# DFI Interface ----------------------------------------------------------------------------
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self.dfi = Interface(addressbits, bankbits, nranks, 4*databits, 4)
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# Debugging
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self.dq_i_data = []
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# # #
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bl8_sel = Signal()
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@ -301,8 +259,8 @@ class ECP5DDRPHY(Module, AutoCSR):
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i_SCLK=ClockSignal("sys"),
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i_ECLK=ClockSignal("sys2x"),
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i_RST=ResetSignal("sys2x"),
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i_DDRDEL=self.ddrdel,
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i_PAUSE=self.pause | self._dly_sel.storage[i],
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i_DDRDEL=self.init.delay,
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i_PAUSE=self.init.pause | self._dly_sel.storage[i],
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# Control
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# Assert LOADNs to use DDRDEL control
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@ -328,12 +286,21 @@ class ECP5DDRPHY(Module, AutoCSR):
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o_WRPNTR1=wrpntr[1],
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o_WRPNTR2=wrpntr[2],
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o_DATAVALID=self.datavalid[i],
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o_BURSTDET=self.burstdet[i],
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o_BURSTDET=burstdet,
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# Writes (generate shifted ECLK clock for writes)
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o_DQSW270=dqsw270,
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o_DQSW=dqsw
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)
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burstdet_d = Signal()
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self.sync += [
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burstdet_d.eq(burstdet),
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If(self._burstdet_clr.re,
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self._burstdet_seen.status[i].eq(0)
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).Elif(burstdet & ~burstdet_d,
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self._burstdet_seen.status[i].eq(1)
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)
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]
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# DQS and DM ---------------------------------------------------------------------------
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dqs_serdes_pattern = Signal(8, reset=0b1010)
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