litedram/frontend/bist: cleanup and add ticks counters to measure performance with hardware
This commit is contained in:
Florent Kermarrec
parent
6091c6de60
commit
c8713bfb48
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@ -20,16 +20,15 @@ class LFSR(Module):
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n_out : int
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Width of the output data signal.
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n_state : int
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???
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LFSR internal state
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taps : list of int
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???
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LFSR taps (from polynom)
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Attributes
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----------
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o : in
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Output data
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"""
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def __init__(self, n_out, n_state=31, taps=[27, 30]):
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self.o = Signal(n_out)
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@ -63,7 +62,6 @@ class Counter(Module):
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o : in
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Output data
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"""
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def __init__(self, n_out):
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self.o = Signal(n_out)
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@ -74,40 +72,44 @@ class Counter(Module):
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@ResetInserter()
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class _LiteDRAMBISTGenerator(Module):
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def __init__(self, dram_port, random):
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self.start = Signal()
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self.done = Signal()
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self.base = Signal(dram_port.aw)
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self.length = Signal(dram_port.aw)
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self.ticks = Signal(32)
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# # #
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self.submodules.dma = dma = LiteDRAMDMAWriter(dram_port)
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gen_cls = LFSR if random else Counter
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self.submodules.gen = gen = gen_cls(dram_port.dw)
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gen = gen_cls(dram_port.dw)
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dma = LiteDRAMDMAWriter(dram_port)
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self.submodules += dma, gen
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self.cmd_counter = cmd_counter = Signal(dram_port.aw)
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cmd_counter = Signal(dram_port.aw)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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If(self.start,
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NextValue(cmd_counter, 0),
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NextState("RUN")
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),
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NextValue(self.ticks, 0)
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)
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fsm.act("RUN",
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dma.sink.valid.eq(1),
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If(dma.sink.ready,
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gen.ce.eq(1),
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NextValue(cmd_counter, cmd_counter + 1),
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If(cmd_counter == (self.length-1),
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If(cmd_counter == (self.length - 1),
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NextState("DONE")
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),
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)
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),
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NextValue(self.ticks, self.ticks + 1)
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)
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fsm.act("DONE",
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self.done.eq(1),
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self.done.eq(1)
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)
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self.comb += [
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dma.sink.address.eq(self.base + cmd_counter),
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@ -116,7 +118,7 @@ class _LiteDRAMBISTGenerator(Module):
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class LiteDRAMBISTGenerator(Module, AutoCSR):
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"""litex module to generate a given pattern in memory.abs
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"""DRAM memory pattern generator.
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Attributes
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----------
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@ -132,21 +134,25 @@ class LiteDRAMBISTGenerator(Module, AutoCSR):
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done : out
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The module has completed writing the pattern.
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"""
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ticks : out
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Duration of the generation.
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"""
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def __init__(self, dram_port, random=True):
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self.reset = CSR()
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self.start = CSR()
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self.done = CSRStatus()
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self.base = CSRStorage(dram_port.aw)
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self.length = CSRStorage(dram_port.aw)
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self.ticks = CSRStatus(32)
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# # #
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cd = dram_port.cd
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core = _LiteDRAMBISTGenerator(dram_port, random)
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self.submodules.core = ClockDomainsRenamer(cd)(core)
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core = ClockDomainsRenamer(cd)(core)
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self.submodules += core
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reset_sync = PulseSynchronizer("sys", cd)
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start_sync = PulseSynchronizer("sys", cd)
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@ -177,57 +183,66 @@ class LiteDRAMBISTGenerator(Module, AutoCSR):
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core.length.eq(length_sync.o)
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]
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ticks_sync = BusSynchronizer(32, cd, "sys")
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self.submodules += ticks_sync
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self.comb += [
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ticks_sync.i.eq(core.ticks),
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self.ticks.status.eq(ticks_sync.o)
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]
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@ResetInserter()
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class _LiteDRAMBISTChecker(Module, AutoCSR):
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def __init__(self, dram_port, random):
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self.start = Signal()
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self.done = Signal()
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self.base = Signal(dram_port.aw)
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self.length = Signal(dram_port.aw)
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self.ticks = Signal(32)
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self.errors = Signal(32)
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# # #
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self.submodules.dma = dma = LiteDRAMDMAReader(dram_port)
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gen_cls = LFSR if random else Counter
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self.submodules.gen = gen = gen_cls(dram_port.dw)
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gen = gen_cls(dram_port.dw)
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dma = LiteDRAMDMAReader(dram_port)
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self.submodules += dma, gen
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# address
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self.cmd_counter = cmd_counter = Signal(dram_port.aw)
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self.submodules.cmd_fsm = cmd_fsm = FSM(reset_state="IDLE")
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cmd_counter = Signal(dram_port.aw)
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cmd_fsm = FSM(reset_state="IDLE")
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self.submodules += cmd_fsm
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cmd_fsm.act("IDLE",
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If(self.start,
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NextValue(cmd_counter, 0),
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NextState("RUN")
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),
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)
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)
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cmd_fsm.act("RUN",
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dma.sink.valid.eq(1),
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If(dma.sink.ready,
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NextValue(cmd_counter, cmd_counter + 1),
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If(cmd_counter == (self.length-1),
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If(cmd_counter == (self.length - 1),
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NextState("DONE")
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),
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),
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)
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)
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)
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cmd_fsm.act("DONE")
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self.comb += dma.sink.address.eq(self.base + cmd_counter)
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# data
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self.data_counter = data_counter = Signal(dram_port.aw)
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self.submodules.data_fsm = data_fsm = FSM(reset_state="IDLE")
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data_counter = Signal(dram_port.aw)
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data_fsm = FSM(reset_state="IDLE")
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self.submodules += data_fsm
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data_fsm.act("IDLE",
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If(self.start,
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NextValue(data_counter, 0),
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NextValue(self.errors, 0),
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NextState("RUN")
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),
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NextValue(self.ticks, 0)
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)
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data_fsm.act("RUN",
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dma.source.ready.eq(1),
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@ -235,21 +250,21 @@ class _LiteDRAMBISTChecker(Module, AutoCSR):
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gen.ce.eq(1),
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NextValue(data_counter, data_counter + 1),
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If(dma.source.data != gen.o,
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NextValue(self.errors, self.errors + 1),
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NextValue(self.errors, self.errors + 1)
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),
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If(data_counter == (self.length-1),
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If(data_counter == (self.length - 1),
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NextState("DONE")
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),
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)
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),
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NextValue(self.ticks, self.ticks + 1)
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)
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data_fsm.act("DONE",
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self.done.eq(1)
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)
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data_fsm.act("DONE")
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self.comb += self.done.eq(cmd_fsm.ongoing("DONE") &
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data_fsm.ongoing("DONE"))
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class LiteDRAMBISTChecker(Module, AutoCSR):
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"""litex module to check a given pattern in memory.
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"""DRAM memory pattern checker.
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Attributes
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----------
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@ -266,18 +281,19 @@ class LiteDRAMBISTChecker(Module, AutoCSR):
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done : out
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The module has completed checking
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ticks: out
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Duration of the check.
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errors : out
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Number of DRAM words which don't match.
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"""
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def __init__(self, dram_port, random=True):
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self.reset = CSR()
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self.start = CSR()
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self.base = CSRStorage(dram_port.aw)
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self.length = CSRStorage(dram_port.aw)
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self.done = CSRStatus()
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self.ticks = CSRStatus(32)
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self.errors = CSRStatus(32)
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# # #
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@ -285,7 +301,8 @@ class LiteDRAMBISTChecker(Module, AutoCSR):
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cd = dram_port.cd
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core = _LiteDRAMBISTChecker(dram_port, random)
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self.submodules.core = ClockDomainsRenamer(cd)(core)
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core = ClockDomainsRenamer(cd)(core)
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self.submodules += core
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reset_sync = PulseSynchronizer("sys", cd)
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start_sync = PulseSynchronizer("sys", cd)
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@ -316,6 +333,13 @@ class LiteDRAMBISTChecker(Module, AutoCSR):
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core.length.eq(length_sync.o)
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]
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ticks_sync = BusSynchronizer(32, cd, "sys")
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self.submodules += ticks_sync
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self.comb += [
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ticks_sync.i.eq(core.ticks),
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self.ticks.status.eq(ticks_sync.o)
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]
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errors_sync = BusSynchronizer(32, cd, "sys")
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self.submodules += errors_sync
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self.comb += [
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