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frontend: dma_lasmi --> dma, wishbone2lasmi --> bridge

This commit is contained in:
Florent Kermarrec 2016-04-29 17:42:07 +02:00
parent 97fb293109
commit c8d2850e8c
2 changed files with 40 additions and 41 deletions
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27
litedram/frontend/wishbone2lasmi.py → litedram/frontend/bridge.py
View File

@ -1,11 +1,10 @@
from litex.gen import * from litex.gen import *
from litex.gen.genlib.fsm import FSM, NextState
class WB2LASMI(Module): class LiteDRAMWishboneBridge(Module):
def __init__(self, wishbone, lasmim): def __init__(self, wishbone, port):
### # # #
# Control FSM # Control FSM
self.submodules.fsm = fsm = FSM(reset_state="IDLE") self.submodules.fsm = fsm = FSM(reset_state="IDLE")
@ -15,9 +14,9 @@ class WB2LASMI(Module):
) )
) )
fsm.act("REQUEST", fsm.act("REQUEST",
lasmim.stb.eq(1), port.stb.eq(1),
lasmim.we.eq(wishbone.we), port.we.eq(wishbone.we),
If(lasmim.req_ack, If(port.req_ack,
If(wishbone.we, If(wishbone.we,
NextState("WRITE_DATA") NextState("WRITE_DATA")
).Else( ).Else(
@ -26,14 +25,14 @@ class WB2LASMI(Module):
) )
) )
fsm.act("WRITE_DATA", fsm.act("WRITE_DATA",
If(lasmim.dat_w_ack, If(port.dat_w_ack,
lasmim.dat_we.eq(wishbone.sel), port.dat_we.eq(wishbone.sel),
wishbone.ack.eq(1), wishbone.ack.eq(1),
NextState("IDLE") NextState("IDLE")
) )
) )
fsm.act("READ_DATA", fsm.act("READ_DATA",
If(lasmim.dat_r_ack, If(port.dat_r_ack,
wishbone.ack.eq(1), wishbone.ack.eq(1),
NextState("IDLE") NextState("IDLE")
) )
@ -41,9 +40,9 @@ class WB2LASMI(Module):
# Address / Datapath # Address / Datapath
self.comb += [ self.comb += [
lasmim.adr.eq(wishbone.adr), port.adr.eq(wishbone.adr),
If(lasmim.dat_w_ack, If(port.dat_w_ack,
lasmim.dat_w.eq(wishbone.dat_w), port.dat_w.eq(wishbone.dat_w),
), ),
wishbone.dat_r.eq(lasmim.dat_r) wishbone.dat_r.eq(port.dat_r)
] ]

54
litedram/frontend/dma_lasmi.py → litedram/frontend/dma.py
View File

@ -3,27 +3,27 @@ from litex.gen.genlib.fifo import SyncFIFO
from litex.soc.interconnect import stream from litex.soc.interconnect import stream
class Reader(Module): class LiteDRAMDMAReader(Module):
def __init__(self, lasmim, fifo_depth=None): def __init__(self, port, fifo_depth=None):
self.sink = sink = stream.Endpoint([("address", lasmim.aw)]) self.sink = sink = stream.Endpoint([("address", port.aw)])
self.source = source = stream.Endpoint([("data", lasmim.dw)]) self.source = source = stream.Endpoint([("data", port.dw)])
self.busy = Signal() self.busy = Signal()
# # # # # #
if fifo_depth is None: if fifo_depth is None:
fifo_depth = lasmim.req_queue_size + lasmim.read_latency + 2 fifo_depth = port.req_queue_size + port.read_latency + 2
# request issuance # request issuance
request_enable = Signal() request_enable = Signal()
request_issued = Signal() request_issued = Signal()
self.comb += [ self.comb += [
lasmim.we.eq(0), port.we.eq(0),
lasmim.stb.eq(sink.valid & request_enable), port.stb.eq(sink.valid & request_enable),
lasmim.adr.eq(sink.address), port.adr.eq(sink.address),
sink.ready.eq(lasmim.req_ack & request_enable), sink.ready.eq(port.req_ack & request_enable),
request_issued.eq(lasmim.stb & lasmim.req_ack) request_issued.eq(port.stb & port.req_ack)
] ]
# FIFO reservation level counter # FIFO reservation level counter
@ -44,12 +44,12 @@ class Reader(Module):
] ]
# FIFO # FIFO
fifo = SyncFIFO(lasmim.dw, fifo_depth) fifo = SyncFIFO(port.dw, fifo_depth)
self.submodules += fifo self.submodules += fifo
self.comb += [ self.comb += [
fifo.din.eq(lasmim.dat_r), fifo.din.eq(port.dat_r),
fifo.we.eq(lasmim.dat_r_ack), fifo.we.eq(port.dat_r_ack),
source.valid.eq(fifo.readable), source.valid.eq(fifo.readable),
fifo.re.eq(source.ready), fifo.re.eq(source.ready),
@ -58,34 +58,34 @@ class Reader(Module):
] ]
class Writer(Module): class LiteDRAMDMAWriter(Module):
def __init__(self, lasmim, fifo_depth=None): def __init__(self, port, fifo_depth=None):
self.source = source = stream.Endpoint([("address", lasmim.aw), self.source = source = stream.Endpoint([("address", port.aw),
("data", lasmim.dw)]) ("data", port.dw)])
self.busy = Signal() self.busy = Signal()
# # # # # #
if fifo_depth is None: if fifo_depth is None:
fifo_depth = lasmim.req_queue_size + lasmim.write_latency + 2 fifo_depth = port.req_queue_size + port.write_latency + 2
fifo = SyncFIFO(lasmim.dw, fifo_depth) fifo = SyncFIFO(port.dw, fifo_depth)
self.submodules += fifo self.submodules += fifo
self.comb += [ self.comb += [
lasmim.we.eq(1), port.we.eq(1),
lasmim.stb.eq(fifo.writable & source.valid), port.stb.eq(fifo.writable & source.valid),
lasmim.adr.eq(source.address), port.adr.eq(source.address),
source.ready.eq(fifo.writable & lasmim.req_ack), source.ready.eq(fifo.writable & port.req_ack),
fifo.we.eq(source.valid & lasmim.req_ack), fifo.we.eq(source.valid & port.req_ack),
fifo.din.eq(source.data) fifo.din.eq(source.data)
] ]
self.comb += [ self.comb += [
If(lasmim.dat_w_ack, If(port.dat_w_ack,
fifo.re.eq(1), fifo.re.eq(1),
lasmim.dat_we.eq(2**(lasmim.dw//8)-1), port.dat_we.eq(2**(port.dw//8)-1),
lasmim.dat_w.eq(fifo.dout) port.dat_w.eq(fifo.dout)
), ),
self.busy.eq(fifo.readable) self.busy.eq(fifo.readable)
] ]