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phy/s7ddrphy: handle cmd_latency properly (add it to rd/wrphase).

This commit is contained in:
Florent Kermarrec 2020-09-30 19:45:23 +02:00
parent b1c26d996f
commit c8f1e80215
1 changed files with 10 additions and 11 deletions
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21
litedram/phy/usddrphy.py
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@ -49,12 +49,11 @@ class USDDRPHY(Module, AutoCSR):
if phytype == "USDDRPHY": assert iodelay_clk_freq >= 200e6 if phytype == "USDDRPHY": assert iodelay_clk_freq >= 200e6
if phytype == "USPDDRPHY": assert iodelay_clk_freq >= 300e6 if phytype == "USPDDRPHY": assert iodelay_clk_freq >= 300e6
cl, cwl = get_cl_cw(memtype, tck) cl, cwl = get_cl_cw(memtype, tck)
cwl = cwl + cmd_latency cl_sys_latency = get_sys_latency(nphases, cl)
cl_sys_latency = get_sys_latency(nphases, cl) cwl_sys_latency = get_sys_latency(nphases, cwl)
cwl_sys_latency = get_sys_latency(nphases, cwl) rdphase = get_sys_phase(nphases, cl_sys_latency, cl + cmd_latency)
rdcmdphase, rdphase = get_sys_phases(nphases, cl_sys_latency, cl) wrphase = get_sys_phase(nphases, cwl_sys_latency, cwl + cmd_latency)
wrcmdphase, wrphase = get_sys_phases(nphases, cwl_sys_latency, cwl)
# Registers -------------------------------------------------------------------------------- # Registers --------------------------------------------------------------------------------
self._rst = CSRStorage() self._rst = CSRStorage()
@ -100,12 +99,12 @@ class USDDRPHY(Module, AutoCSR):
dfi_databits = 2*databits, dfi_databits = 2*databits,
nranks = nranks, nranks = nranks,
nphases = nphases, nphases = nphases,
rdphase = rdphase, rdphase = _rdphase,
wrphase = wrphase, wrphase = _wrphase,
rdcmdphase = rdcmdphase, rdcmdphase = _rdcmdphase,
wrcmdphase = wrcmdphase, wrcmdphase = _wrcmdphase,
cl = cl, cl = cl,
cwl = cwl - cmd_latency, cwl = cwl,
read_latency = cl_sys_latency + 5, read_latency = cl_sys_latency + 5,
write_latency = cwl_sys_latency, write_latency = cwl_sys_latency,
cmd_latency = cmd_latency, cmd_latency = cmd_latency,