i think there's a missing "self" in the params

2018-08-21 17:28:42 +08:00 · 2018-08-21 17:28:42 +08:00 · c9b8db5dc9
parent 0b6e21ab6d
commit c9b8db5dc9
1 changed files with 1 additions and 1 deletions
--- a/litedram/common.py
+++ b/litedram/common.py
@ -26,7 +26,7 @@ class PhySettings:
        self.cwl = cwl

    # Optional DDR3 electrical settings
-    def add_electrical_settings(rtt_nom, rtt_wr, ron):
+    def add_electrical_settings(self, rtt_nom, rtt_wr, ron):
        assert self.memtype == "DDR3"
        self.rtt_nom = rtt_nom # Non-Writes on-die termination impedance
        self.rtt_wr = rtt_wr   # Writes on-die termination impedance