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continue cleanup

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This commit is contained in:
Florent Kermarrec 2016-05-02 09:48:17 +02:00
parent f37fc3d854
commit cbe9748fa1
5 changed files with 30 additions and 30 deletions
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2
litedram/common.py
View file

@ -97,7 +97,7 @@ class CommandRequestRW(CommandRequest):
def __init__(self, a, ba):
CommandRequest.__init__(self, a, ba)
self.valid = Signal()
self.ack = Signal()
self.ready = Signal()
self.is_cmd = Signal()
self.is_read = Signal()
self.is_write = Signal()

27
litedram/core/bankmachine.py
View file

@ -28,7 +28,8 @@ class _AddressSlicer:
class BankMachine(Module):
def __init__(self, geom_settings, timing_settings, controller_settings, address_align, bankn, req):
def __init__(self, aw, n, address_align, geom_settings, timing_settings, controller_settings):
self.req = req = Record(cmd_layout(aw))
self.refresh_req = Signal()
self.refresh_gnt = Signal()
self.cmd = CommandRequestRW(geom_settings.addressbits, geom_settings.bankbits)
@ -36,15 +37,11 @@ class BankMachine(Module):
# # #
# Request FIFO
layout = [("we", 1), ("adr", len(req.adr))]
fifo = stream.SyncFIFO(layout, controller_settings.req_queue_size)
fifo = stream.SyncFIFO([("we", 1), ("adr", len(req.adr))],
controller_settings.req_queue_size)
self.submodules += fifo
self.comb += [
fifo.sink.valid.eq(req.valid),
fifo.sink.we.eq(req.we),
fifo.sink.adr.eq(req.adr),
req.ready.eq(fifo.sink.ready),
req.connect(fifo.sink, omit=["dat_w_ack", "dat_r_ack", "lock"]),
fifo.source.ready.eq(req.dat_w_ack | req.dat_r_ack),
req.lock.eq(fifo.source.valid),
]
@ -71,7 +68,7 @@ class BankMachine(Module):
# Address generation
s_row_adr = Signal()
self.comb += [
self.cmd.ba.eq(bankn),
self.cmd.ba.eq(n),
If(s_row_adr,
self.cmd.a.eq(slicer.row(fifo.source.adr))
).Else(
@ -82,7 +79,7 @@ class BankMachine(Module):
# Respect write-to-precharge specification
self.submodules.precharge_timer = WaitTimer(2 + timing_settings.tWR - 1 + 1)
self.comb += self.precharge_timer.wait.eq(~(self.cmd.valid &
self.cmd.ack &
self.cmd.ready &
self.cmd.is_write))
# Control and command generation FSM
@ -96,10 +93,10 @@ class BankMachine(Module):
# NB: write-to-read specification is enforced by multiplexer
self.cmd.valid.eq(1),
If(fifo.source.we,
req.dat_w_ack.eq(self.cmd.ack),
req.dat_w_ack.eq(self.cmd.ready),
self.cmd.is_write.eq(1)
).Else(
req.dat_r_ack.eq(self.cmd.ack),
req.dat_r_ack.eq(self.cmd.ready),
self.cmd.is_read.eq(1)
),
self.cmd.cas_n.eq(0),
@ -119,7 +116,7 @@ class BankMachine(Module):
# to assert track_close.
If(self.precharge_timer.done,
self.cmd.valid.eq(1),
If(self.cmd.ack,
If(self.cmd.ready,
NextState("TRP")
),
self.cmd.ras_n.eq(0),
@ -132,7 +129,9 @@ class BankMachine(Module):
track_open.eq(1),
self.cmd.valid.eq(1),
self.cmd.is_cmd.eq(1),
If(self.cmd.ack, NextState("TRCD")),
If(self.cmd.ready,
NextState("TRCD")
),
self.cmd.ras_n.eq(0)
)
fsm.act("REFRESH",

15
litedram/core/controller.py
View file

@ -41,7 +41,6 @@ class LiteDRAMController(Module):
req_queue_size=controller_settings.req_queue_size,
read_latency=phy_settings.read_latency+1,
write_latency=phy_settings.write_latency+1)
self.nrowbits = geom_settings.colbits - address_align
# # #
@ -49,19 +48,21 @@ class LiteDRAMController(Module):
self.submodules.refresher = Refresher(geom_settings.addressbits,
geom_settings.bankbits,
timing_settings.tRP,
timing_settings.tREFI,timing_settings.tRFC,
timing_settings.tREFI,
timing_settings.tRFC,
controller_settings.with_refresh)
bank_machines = []
for i in range(2**geom_settings.bankbits):
bank_machine = BankMachine(geom_settings,
timing_settings,
controller_settings,
address_align,
bank_machine = BankMachine(self.lasmic.aw,
i,
getattr(self.lasmic, "bank"+str(i)))
address_align,
geom_settings,
timing_settings,
controller_settings)
bank_machines.append(bank_machine)
self.submodules += bank_machine
self.comb += getattr(self.lasmic, "bank"+str(i)).connect(bank_machine.req)
self.submodules.multiplexer = Multiplexer(phy_settings,
geom_settings,

12
litedram/core/multiplexer.py
View file

@ -41,9 +41,9 @@ class _CommandChooser(Module):
& ((self.cmd.is_cmd & self.want_cmds) | ((self.cmd.is_read == self.want_reads) \
& (self.cmd.is_write == self.want_writes))))
self.comb += [If(self.cmd.valid & self.cmd.ack & (rr.grant == i), req.ack.eq(1))
self.comb += [If(self.cmd.valid & self.cmd.ready & (rr.grant == i), req.ready.eq(1))
for i, req in enumerate(requests)]
self.comb += rr.ce.eq(self.cmd.ack)
self.comb += rr.ce.eq(self.cmd.ready)
class _Steerer(Module):
@ -171,8 +171,8 @@ class Multiplexer(Module, AutoCSR):
fsm.act("READ",
read_time_en.eq(1),
choose_req.want_reads.eq(1),
choose_cmd.cmd.ack.eq(1),
choose_req.cmd.ack.eq(1),
choose_cmd.cmd.ready.eq(1),
choose_req.cmd.ready.eq(1),
steerer_sel(steerer, phy_settings, "read"),
If(write_available,
# TODO: switch only after several cycles of ~read_available?
@ -183,8 +183,8 @@ class Multiplexer(Module, AutoCSR):
fsm.act("WRITE",
write_time_en.eq(1),
choose_req.want_writes.eq(1),
choose_cmd.cmd.ack.eq(1),
choose_req.cmd.ack.eq(1),
choose_cmd.cmd.ready.eq(1),
choose_req.cmd.ready.eq(1),
steerer_sel(steerer, phy_settings, "write"),
If(read_available,
If(~write_available | max_write_time, NextState("WTR"))

4
litedram/frontend/bist.py
View file

@ -65,7 +65,7 @@ class LiteDRAMBISTGenerator(Module):
self.comb += [
self._dma.trigger.eq(self._shoot.re),
self._dma.data.valid.eq(en),
lfsr.ce.eq(en & self._dma.data.ack),
lfsr.ce.eq(en & self._dma.data.ready),
self._dma.data.d.eq(lfsr.o)
]
@ -91,7 +91,7 @@ class LiteDRAMBISTChecker(Module):
self.comb += [
lfsr.ce.eq(self._dma.data.valid),
self._dma.data.ack.eq(1)
self._dma.data.ready.eq(1)
]
err_cnt = self._error_count.status
self.sync += [