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examples: add sdram_rank_nb and user_ports_id_width

This commit is contained in:
Florent Kermarrec 2018-09-07 17:55:46 +02:00
parent 849b1f6c35
commit cc481be81f
3 changed files with 10 additions and 5 deletions
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4
examples/arty_config.py
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@ -8,6 +8,7 @@ core_config = {
# modules / phy
"sdram_module": MT41K128M16,
"sdram_module_nb": 1,
"sdram_rank_nb": 1,
"sdram_phy": A7DDRPHY,
# electrical
@ -28,5 +29,6 @@ core_config = {
# user_ports
"user_ports_nb": 1,
"user_ports_type": "axi"
"user_ports_type": "axi",
"user_ports_id_width": 8
}

4
examples/genesys2_config.py
View File

@ -8,6 +8,7 @@ core_config = {
# modules / phy
"sdram_module": MT41J256M16,
"sdram_module_nb": 2,
"sdram_rank_nb": 1,
"sdram_phy": K7DDRPHY,
# electrical
@ -28,5 +29,6 @@ core_config = {
# user_ports
"user_ports_nb": 1,
"user_ports_type": "axi"
"user_ports_type": "axi",
"user_ports_id_width": 8
}

7
examples/litedram_gen.py
View File

@ -59,7 +59,8 @@ def get_dram_ios(core_config):
Subsignal("ras_n", Pins("X")),
Subsignal("cas_n", Pins("X")),
Subsignal("we_n", Pins("X")),
Subsignal("cs_n", Pins("X")),
Subsignal("cs_n", Pins(
"X "*core_config["sdram_rank_nb"])),
Subsignal("dm", Pins(
"X "*2*core_config["sdram_module_nb"])),
Subsignal("dq", Pins(
@ -83,7 +84,7 @@ def get_native_user_port_ios(_id, aw, dw):
Subsignal("cmd_valid", Pins(1)),
Subsignal("cmd_ready", Pins(1)),
Subsignal("cmd_we", Pins(1)),
Subsignal("cmd_adr", Pins(aw)),
Subsignal("cmd_addr", Pins(aw)),
# wdata
Subsignal("wdata_valid", Pins(1)),
@ -312,7 +313,7 @@ class LiteDRAMCore(SoCSDRAM):
user_port.cmd.valid.eq(_user_port_io.cmd_valid),
_user_port_io.cmd_ready.eq(user_port.cmd.ready),
user_port.cmd.we.eq(_user_port_io.cmd_we),
user_port.cmd.adr.eq(_user_port_io.cmd_adr),
user_port.cmd.addr.eq(_user_port_io.cmd_addr),
# wdata
user_port.wdata.valid.eq(_user_port_io.wdata_valid),