Merge pull request #77 from daveshah1/ecp5_75MHz

ecp5ddrphy: Shift read position forwards to fix higher frequencies
2019-03-02 22:34:12 +01:00 · 2019-03-02 22:34:12 +01:00 · cec35f3efd
parent 6715c1bd45 fa26dcdcb0
commit cec35f3efd
1 changed files with 1 additions and 1 deletions
--- a/litedram/phy/ecp5ddrphy.py
+++ b/litedram/phy/ecp5ddrphy.py
@ -499,7 +499,7 @@ class ECP5DDRPHY(Module, AutoCSR):
            rddata_en = n_rddata_en
        self.sync += [phase.rddata_valid.eq(rddata_en)
            for phase in self.dfi.phases]
-        self.comb += dqs_read.eq(rddata_ens[cl_sys_latency] | rddata_ens[cl_sys_latency+1])
+        self.comb += dqs_read.eq(rddata_ens[cl_sys_latency+1] | rddata_ens[cl_sys_latency+2])
        oe = Signal()
        last_wrdata_en = Signal(cwl_sys_latency+3)
        wrphase = self.dfi.phases[self.settings.wrphase]