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modules: add M12L64322A

This commit is contained in:
Florent Kermarrec 2020-01-18 21:16:19 +01:00
parent 6105ae371e
commit cee3a43685
1 changed files with 10 additions and 0 deletions
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litedram/modules.py
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@ -200,6 +200,16 @@ class AS4C32M8(SDRAMModule):
technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 15)) technology_timings = _TechnologyTimings(tREFI=64e6/8192, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 15))
speedgrade_timings = {"default": _SpeedgradeTimings(tRP=20, tRCD=20, tWR=15, tRFC=(None, 66), tFAW=None, tRAS=44)} speedgrade_timings = {"default": _SpeedgradeTimings(tRP=20, tRCD=20, tWR=15, tRFC=(None, 66), tFAW=None, tRAS=44)}
class M12L64322A(SDRAMModule):
memtype = "SDR"
# geometry
nbanks = 4
nrows = 2048
ncols = 256
# timings
technology_timings = _TechnologyTimings(tREFI=64e6/4096, tWTR=(2, None), tCCD=(1, None), tRRD=(None, 10))
speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=15, tRFC=(None, 55), tFAW=None, tRAS=40)}
# DDR ---------------------------------------------------------------------------------------------- # DDR ----------------------------------------------------------------------------------------------
class MT46V32M16(SDRAMModule): class MT46V32M16(SDRAMModule):