Merge branch 'master' of http://github.com/enjoy-digital/litedram

litedram/common.py

@@ -26,7 +26,7 @@ class PhySettings:
         self.cwl = cwl
 
     # Optional DDR3 electrical settings
-    def add_electrical_settings(rtt_nom, rtt_wr, ron):
+    def add_electrical_settings(self, rtt_nom, rtt_wr, ron):
         assert self.memtype == "DDR3"
         self.rtt_nom = rtt_nom # Non-Writes on-die termination impedance
         self.rtt_wr = rtt_wr   # Writes on-die termination impedance

litedram/modules.py

@@ -356,3 +356,29 @@ class MT18KSF1G72HZ(SDRAMModule):
     tWR  = tWR_1600
     tRFC = tRFC_1600
     tFAW = tFAW_1600
+
+
+class K4B2G1646FBCK0(SDRAMModule):  ### TODO: optimize and revalidate all timings, at cold and hot temperatures
+    memtype = "DDR3"
+    # geometry
+    nbanks = 8
+    nrows  = 16384
+    ncols  = 1024
+    # speedgrade invariant timings
+    tREFI = 7800  # 3900 refresh more often at 85C+
+    tWTR  = (14, 35)
+    tCCD  = (4, None)
+    tRRD  = 10  # 4 * clk = 10ns
+    # speedgrade related timings
+    # DDR3-1600
+    tRP_1600  = 13.125
+    tRCD_1600 = 13.125
+    tWR_1600  = 35  # this is hard-coded in MR0 to be 14 cycles, 14 * 2.5 = 35, see sdram_init.py@L224
+    tRFC_1600 = 160
+    tFAW_1600 = (None, 40)
+    # API retro-compatibility
+    tRP  = tRP_1600
+    tRCD = tRCD_1600
+    tWR  = tWR_1600
+    tRFC = tRFC_1600
+    tFAW = tFAW_1600