test: check converters at higher data width ratios

test/common.py

@@ -566,6 +566,17 @@ class MemoryTestDataMixin:
                     0x0000000000000000000000000000000000000000000000000000000000000000,  # 0x60
                 ]
             ),
+            "8bit_to_256bit":  dict(
+                #       address, data
+                pattern=[(i, 0x10 + i) for i in range(128)],
+                expected=[
+                    # data, address
+                    0x2f2e2d2c2b2a292827262524232221201f1e1d1c1b1a19181716151413121110,  # 0x00
+                    0x4f4e4d4c4b4a494847464544434241403f3e3d3c3b3a39383736353433323130,  # 0x20
+                    0x6f6e6d6c6b6a696867666564636261605f5e5d5c5b5a59585756555453525150,  # 0x40
+                    0x8f8e8d8c8b8a898887868584838281807f7e7d7c7b7a79787776757473727170,  # 0x60
+                ]
+            ),
             "32bit_to_256bit_not_aligned":  dict(
                 pattern=[
                     # address, data
@@ -690,5 +701,9 @@ class MemoryTestDataMixin:
             pattern  = data["32bit_to_128bit"]["pattern"].copy(),
             expected = half_width(data["32bit_to_128bit"]["expected"], from_width=128),
         )
+        data["8bit_to_128bit"] = dict(
+            pattern  = data["8bit_to_256bit"]["pattern"].copy(),
+            expected = half_width(data["8bit_to_256bit"]["expected"], from_width=256),
+        )
 
         return data

test/test_adaptation.py

@@ -118,7 +118,7 @@ class TestAdapter(MemoryTestDataMixin, unittest.TestCase):
             dut.memory.read_handler(dut.read_crossbar_port),
             timeout_generator(1000),
         ]
-        run_simulation(dut, generators, vcd_name='sim.vcd')
+        run_simulation(dut, generators)
         self.assertEqual(dut.memory.mem, mem_expected)
         self.assertEqual(dut.read_driver.rdata, [data for adr, data in pattern])
 
@@ -158,6 +158,14 @@ class TestAdapter(MemoryTestDataMixin, unittest.TestCase):
         # Verify 32-bit to 256-bit up-conversion.
         self.converter_test(test_data="32bit_to_256bit", user_data_width=32, native_data_width=256)
 
+    def test_converter_1to16(self):
+        # Verify 32-bit to 256-bit up-conversion.
+        self.converter_test(test_data="8bit_to_128bit", user_data_width=8, native_data_width=128)
+
+    def test_converter_1to32(self):
+        # Verify 32-bit to 256-bit up-conversion.
+        self.converter_test(test_data="8bit_to_256bit", user_data_width=8, native_data_width=256)
+
     def test_up_converter_read_latencies(self):
         # Verify that up-conversion works with different port reader latencies
         cases = {

test/test_wishbone.py

@@ -93,6 +93,20 @@ class TestWishbone(MemoryTestDataMixin, unittest.TestCase):
         port = LiteDRAMNativePort("both", address_width=30, data_width=64)
         self.wishbone_readback_test(data["pattern"], data["expected"], wb, port)
 
+    def test_wishbone_32bit_to_128bit(self):
+        # Verify Wishbone with 32-bit data width up-converted to 128-bit data width.
+        data = self.pattern_test_data["32bit_to_128bit"]
+        wb   = wishbone.Interface(adr_width=30, data_width=32)
+        port = LiteDRAMNativePort("both", address_width=30, data_width=128)
+        self.wishbone_readback_test(data["pattern"], data["expected"], wb, port)
+
+    def test_wishbone_32bit_to_256bit(self):
+        # Verify Wishbone with 32-bit data width up-converted to 128-bit data width.
+        data = self.pattern_test_data["32bit_to_256bit"]
+        wb   = wishbone.Interface(adr_width=30, data_width=32)
+        port = LiteDRAMNativePort("both", address_width=30, data_width=256)
+        self.wishbone_readback_test(data["pattern"], data["expected"], wb, port)
+
     def test_wishbone_32bit_base_address(self):
         # Verify Wishbone with 32-bit data width and non-zero base address.
         data   = self.pattern_test_data["32bit"]