add 400MHz tap setting (valid for -3 and -2/2E speed grades)

2018-08-09 03:04:34 +08:00 · 2018-08-09 03:04:34 +08:00 · d986b60e03
parent f0f067fe7d
commit d986b60e03
1 changed files with 2 additions and 0 deletions
--- a/litedram/phy/s7ddrphy.py
+++ b/litedram/phy/s7ddrphy.py
@ -76,7 +76,9 @@ class S7DDRPHY(Module, AutoCSR):
        iodelay_tap_average = {
            200e6: 78e-12,
            300e6: 52e-12,
+            400e6: 39e-12,
        }
+
        half_sys8x_taps = math.floor(tck/(4*iodelay_tap_average[iodelay_clk_freq]))
        self._half_sys8x_taps = CSRStorage(4, reset=half_sys8x_taps)