phy/gw5ddrphy: introducing GW5A DDR phy
This commit is contained in:
Gwenhael Goavec-Merou
parent
4dec115023
commit
da78fca00e
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@ -6,6 +6,7 @@ from litedram.phy.usddrphy import USDDRPHY, USPDDRPHY
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from litedram.phy.ecp5ddrphy import ECP5DDRPHY, ECP5DDRPHYInit
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from litedram.phy.gw2ddrphy import GW2DDRPHY
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from litedram.phy.gw5ddrphy import GW5DDRPHY
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# backward compatibility (remove when no longer needed)
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from litedram.phy import s7ddrphy as a7ddrphy
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@ -0,0 +1,484 @@
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#
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# This file is part of LiteDRAM.
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#
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# Copyright (c) 2019 David Shah <dave@ds0.me>
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# Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2022 Icenowy Zheng <icenowy@aosc.io>
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# Copyright (c) 2023 Gwenhael Goavec-Merou <gwenhael@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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# 1:2 frequency-ratio DDR3 PHY for Gowin's GW5A
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# DDR3: 800 MT/s
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from functools import reduce
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from operator import or_
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import math
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from migen import *
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from litex.gen import *
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from migen.fhdl.specials import Tristate
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from migen.genlib.cdc import MultiReg
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from litex.gen.genlib.misc import timeline
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from litex.soc.interconnect.csr import *
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from litedram.common import *
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from litedram.phy.dfi import *
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# BitSlip ------------------------------------------------------------------------------------------
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# FIXME: Use BitSlip from litedram.common.
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class BitSlip(Module):
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def __init__(self, dw, rst=None, slp=None, cycles=1):
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self.i = Signal(dw)
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self.o = Signal(dw)
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self.rst = Signal() if rst is None else rst
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self.slp = Signal() if slp is None else slp
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# # #
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value = Signal(max=cycles*dw)
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self.sync += If(self.slp, value.eq(value + 1))
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self.sync += If(self.rst, value.eq(0))
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r = Signal((cycles+1)*dw, reset_less=True)
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self.sync += r.eq(Cat(r[dw:], self.i))
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cases = {}
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for i in range(cycles*dw):
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cases[i] = self.o.eq(r[i:dw+i])
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self.comb += Case(value, cases)
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# Gowin GW5A DDR PHY Initialization -----------------------------------------------------------------
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class GW5DDRPHYInit(Module):
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def __init__(self):
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self.pause = Signal()
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self.stop = Signal()
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self.delay = Signal(8)
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self.reset = Signal()
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# # #
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new_lock = Signal()
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update = Signal()
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stop = Signal()
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freeze = Signal()
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pause = Signal()
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reset = Signal()
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# DDRDLLA instance -------------------------------------------------------------------------
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_lock = Signal()
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delay = Signal(8)
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self.specials += Instance("DDRDLL",
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p_SCAL_EN = "false",
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i_RESET = ResetSignal("init"),
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i_CLKIN = ClockSignal("sys2x"),
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i_UPDNCNTL = ~update,
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i_STOP = freeze,
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o_STEP = delay,
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o_LOCK = _lock
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)
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lock = Signal()
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lock_d = Signal()
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self.specials += MultiReg(_lock, lock, "init")
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self.sync.init += lock_d.eq(lock)
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self.comb += new_lock.eq(lock & ~lock_d)
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# DDRDLLA/DDQBUFM/ECLK initialization sequence ---------------------------------------------
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t = 8 # in cycles
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self.sync.init += [
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# Wait DDRDLLA Lock
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timeline(new_lock, [
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( 1*t, [freeze.eq(1)]), # Freeze DDRDLLA
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( 2*t, [ stop.eq(1)]), # Stop ECLK domain
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( 3*t, [ reset.eq(1)]), # Reset ECLK domain
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( 4*t, [ reset.eq(0)]), # Release ECLK domain reset
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( 5*t, [ stop.eq(0)]), # Release ECLK domain stop
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( 6*t, [freeze.eq(0)]), # Release DDRDLLA freeze
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( 7*t, [ pause.eq(1)]), # Pause DQSBUFM
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( 8*t, [update.eq(1)]), # Update DDRDLLA
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( 9*t, [update.eq(0)]), # Release DDRDMMA update
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(10*t, [ pause.eq(0)]), # Release DQSBUFM pause
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])
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]
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# ------------------------------------------------------------------------------------------
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self.comb += [
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self.pause.eq(pause),
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self.stop.eq(stop),
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self.delay.eq(delay),
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self.reset.eq(reset),
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]
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# Gowin GW5A DDR PHY -------------------------------------------------------------------------------
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class GW5DDRPHY(Module, AutoCSR):
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def __init__(self, pads,
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sys_clk_freq = 100e6,
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cl = None,
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cwl = None,
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cmd_delay = 0,
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clk_polarity = 0,
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dm_remapping = None):
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assert isinstance(cmd_delay, int) and cmd_delay < 128
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pads = PHYPadsCombiner(pads)
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memtype = "DDR3"
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tck = 2/(2*2*sys_clk_freq)
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addressbits = len(pads.a)
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bankbits = len(pads.ba)
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nranks = 1 if not hasattr(pads, "cs_n") else len(pads.cs_n)
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databits = len(pads.dq)
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nphases = 2
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if not dm_remapping:
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dm_remapping = {}
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assert databits%8 == 0
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# Init -------------------------------------------------------------------------------------
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self.submodules.init = GW5DDRPHYInit()
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# Parameters -------------------------------------------------------------------------------
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cl = get_default_cl( memtype, tck) if cl is None else cl
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cwl = get_default_cwl(memtype, tck) if cwl is None else cwl
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cl_sys_latency = get_sys_latency(nphases, cl)
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cwl_sys_latency = get_sys_latency(nphases, cwl)
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# Registers --------------------------------------------------------------------------------
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self._dly_sel = CSRStorage(databits//8)
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self._rdly_dq_rst = CSR()
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self._rdly_dq_inc = CSR()
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self._rdly_dq_bitslip_rst = CSR()
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self._rdly_dq_bitslip = CSR()
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self._burstdet_clr = CSR()
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self._burstdet_seen = CSRStatus(databits//8)
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# Observation
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self.datavalid = Signal(databits//8)
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# PHY settings -----------------------------------------------------------------------------
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rdphase = get_sys_phase(nphases, cl_sys_latency, cl)
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wrphase = get_sys_phase(nphases, cwl_sys_latency, cwl)
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self.settings = PhySettings(
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phytype = "GW5DDRPHY",
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memtype = memtype,
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databits = databits,
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dfi_databits = 4*databits,
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nranks = nranks,
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nphases = nphases,
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rdphase = rdphase,
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wrphase = wrphase,
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cl = cl,
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cwl = cwl,
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read_latency = cl_sys_latency + 9 + 1,
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write_latency = cwl_sys_latency - 1 + 1,
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read_leveling = True,
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bitslips = 4,
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delays = 8,
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)
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# DFI Interface ----------------------------------------------------------------------------
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self.dfi = dfi = Interface(addressbits, bankbits, nranks, 4*databits, nphases)
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# # #
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bl8_chunk = Signal()
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# Iterate on pads groups -------------------------------------------------------------------
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for pads_group in range(len(pads.groups)):
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pads.sel_group(pads_group)
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# Clock --------------------------------------------------------------------------------
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clk_pattern = {0: 0b1010, 1: 0b0101}[clk_polarity]
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for i in range(len(pads.clk_p)):
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pad_oddrx2f = Signal()
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pad_clk = Signal()
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self.specials += Instance("OSER4",
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p_TXCLK_POL = 0b0,
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i_RESET = ResetSignal("sys"),
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i_PCLK = ClockSignal("sys"),
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i_FCLK = ClockSignal("sys2x"),
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**{f"i_TX{n}": 0b0 for n in range(2)},
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**{f"i_D{n}": (clk_pattern >> n) & 0b1 for n in range(4)},
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o_Q0 = pad_oddrx2f,
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o_Q1 = Open()
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)
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self.specials += Instance("IODELAY",
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p_C_STATIC_DLY = cmd_delay,
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p_DYN_DLY_EN = "FALSE",
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p_ADAPT_EN = "FALSE",
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i_SDTAP = 0,
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i_DLYSTEP = Constant(0, 8),
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i_VALUE = 0,
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i_DI = pad_oddrx2f,
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o_DF = Open(),
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o_DO = pad_clk,
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)
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self.specials += Instance("ELVDS_OBUF",
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i_I = pad_clk,
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o_O = pads.clk_p[i],
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o_OB = pads.clk_n[i]
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)
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# Commands -----------------------------------------------------------------------------
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commands = {
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# Pad name: (DFI name, Pad type (required or optional))
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"reset_n" : ("reset_n", "optional"),
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"cs_n" : ("cs_n", "optional"),
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"a" : ("address", "required"),
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"ba" : ("bank" , "required"),
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"ras_n" : ("ras_n" , "required"),
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"cas_n" : ("cas_n" , "required"),
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"we_n" : ("we_n" , "required"),
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"cke" : ("cke" , "optional"),
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"odt" : ("odt" , "optional"),
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}
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for pad_name, (dfi_name, pad_type) in commands.items():
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pad = getattr(pads, pad_name, None)
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if (pad is None):
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if (pad_type == "required"):
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raise ValueError(f"DRAM pad {pad_name} required but not found in pads.")
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continue
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for i in range(len(pad)):
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pad_oddrx2f = Signal()
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self.specials += Instance("OSER4",
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p_TXCLK_POL = 0b0,
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i_RESET = ResetSignal("sys"),
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i_PCLK = ClockSignal("sys"),
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i_FCLK = ClockSignal("sys2x"),
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**{f"i_TX{n}": 0b0 for n in range(2)},
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**{f"i_D{n}": getattr(dfi.phases[n//2], dfi_name)[i] for n in range(4)},
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o_Q0 = pad_oddrx2f,
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o_Q1 = Open()
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)
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self.specials += Instance("IODELAY",
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p_C_STATIC_DLY = cmd_delay,
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p_DYN_DLY_EN = "FALSE",
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p_ADAPT_EN = "FALSE",
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i_SDTAP = 0,
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i_DLYSTEP = Constant(0, 8),
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i_VALUE = 0,
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i_DI = pad_oddrx2f,
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o_DF = Open(),
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o_DO = pad[i]
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)
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# DQS/DM/DQ --------------------------------------------------------------------------------
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dq_oe = Signal()
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dqs_re = Signal()
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dqs_oe = Signal()
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dqs_postamble = Signal()
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dqs_preamble = Signal()
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for i in range(databits//8):
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# DQS
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dqs_i = Signal()
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dqsr90 = Signal()
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dqsw270 = Signal()
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dqsw = Signal()
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rdpntr = Signal(3)
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wrpntr = Signal(3)
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rdly = Signal(3)
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burstdet = Signal()
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self.sync += [
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If(self._dly_sel.storage[i] & self._rdly_dq_rst.re, rdly.eq(0)),
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If(self._dly_sel.storage[i] & self._rdly_dq_inc.re, rdly.eq(rdly + 1))
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]
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self.specials += Instance("DQS",
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p_DQS_MODE = "X2_DDR3",
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# Clocks / Reset
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i_RESET = ResetSignal("sys"),
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i_PCLK = ClockSignal("sys"),
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i_FCLK = ClockSignal("sys2x"),
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i_DLLSTEP = self.init.delay,
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i_HOLD = self.init.pause | self._dly_sel.storage[i],
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# Control
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# Assert LOADNs to use DDRDEL control
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i_RLOADN = 0,
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i_RMOVE = 0,
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i_RDIR = 1,
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i_WLOADN = 0,
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i_WMOVE = 0,
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i_WDIR = 1,
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o_RFLAG = Open(),
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o_WFLAG = Open(),
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# Reads (generate shifted DQS clock for reads)
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i_READ = Replicate(dqs_re, 4),
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i_RCLKSEL = rdly,
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i_DQSIN = dqs_i,
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o_DQSR90 = dqsr90,
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o_RPOINT = rdpntr,
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o_WPOINT = wrpntr,
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o_RVALID = self.datavalid[i],
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o_RBURST = burstdet,
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# Writes (generate shifted ECLK clock for writes)
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i_WSTEP = Constant(0, 8),
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o_DQSW270 = dqsw270,
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o_DQSW0 = dqsw
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)
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burstdet_d = Signal()
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self.sync += [
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burstdet_d.eq(burstdet),
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If(self._burstdet_clr.re, self._burstdet_seen.status[i].eq(0)),
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If(burstdet & ~burstdet_d, self._burstdet_seen.status[i].eq(1)),
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]
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# DQS ----------------------------------------------------------------------------------
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dqs_o = Signal()
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dqs_o_oen = Signal()
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self.specials += [
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Instance("OSER4_MEM",
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p_TCLK_SOURCE = "DQSW",
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p_TXCLK_POL = 0b1,
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i_RESET = ResetSignal("sys"),
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i_PCLK = ClockSignal("sys"),
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i_FCLK = ClockSignal("sys2x"),
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i_TCLK = dqsw,
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i_TX0 = ~(dqs_oe | dqs_postamble),
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i_TX1 = ~(dqs_oe | dqs_preamble),
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**{f"i_D{n}": (0b1010 >> n) & 0b1 for n in range(4)},
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o_Q0 = dqs_o,
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o_Q1 = dqs_o_oen
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),
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Instance("ELVDS_IOBUF",
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i_I = dqs_o,
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i_OEN = dqs_o_oen,
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o_O = dqs_i,
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io_IO = pads.dqs_p[i],
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io_IOB = pads.dqs_n[i]
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)
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]
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# DM -----------------------------------------------------------------------------------
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dm_o_data = Signal(8)
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dm_o_data_d = Signal(8)
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dm_o_data_muxed = Signal(4)
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for n in range(8):
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self.comb += dm_o_data[n].eq(dfi.phases[n//4].wrdata_mask[n%4*databits//8+dm_remapping.get(i, i)])
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self.sync += dm_o_data_d.eq(dm_o_data)
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dm_bl8_cases = {}
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dm_bl8_cases[0] = dm_o_data_muxed.eq(dm_o_data[:4])
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dm_bl8_cases[1] = dm_o_data_muxed.eq(dm_o_data_d[4:])
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self.sync += Case(bl8_chunk, dm_bl8_cases)
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self.specials += Instance("OSER4_MEM",
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p_TCLK_SOURCE = "DQSW270",
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p_TXCLK_POL = 0b0,
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i_RESET = ResetSignal("sys"),
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i_PCLK = ClockSignal("sys"),
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i_FCLK = ClockSignal("sys2x"),
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i_TCLK = dqsw270,
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**{f"i_TX{n}": 0b0 for n in range(2)},
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**{f"i_D{n}": dm_o_data_muxed[n] for n in range(4)},
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o_Q0 = pads.dm[i],
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o_Q1 = Open()
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)
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# DQ -----------------------------------------------------------------------------------
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for j in range(8*i, 8*(i+1)):
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dq_o = Signal()
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dq_o_oen = Signal()
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dq_i = Signal()
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dq_i_data = Signal(8)
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dq_o_data = Signal(8)
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dq_o_data_d = Signal(8)
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dq_o_data_muxed = Signal(4)
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for n in range(8):
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self.comb += dq_o_data[n].eq(dfi.phases[n//4].wrdata[n%4*databits+j])
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self.sync += dq_o_data_d.eq(dq_o_data)
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dq_bl8_cases = {}
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dq_bl8_cases[0] = dq_o_data_muxed.eq(dq_o_data[:4])
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dq_bl8_cases[1] = dq_o_data_muxed.eq(dq_o_data_d[4:])
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self.sync += Case(bl8_chunk, dq_bl8_cases)
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self.specials += Instance("OSER4_MEM",
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p_TCLK_SOURCE = "DQSW270",
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p_TXCLK_POL = 0b0,
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i_RESET = ResetSignal("sys"),
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i_PCLK = ClockSignal("sys"),
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i_FCLK = ClockSignal("sys2x"),
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i_TCLK = dqsw270,
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i_TX0 = ~dq_oe,
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i_TX1 = ~dq_oe,
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**{f"i_D{n}": dq_o_data_muxed[n] for n in range(4)},
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o_Q0 = dq_o,
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o_Q1 = dq_o_oen,
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)
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dq_i_bitslip = BitSlip(4,
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rst = self._dly_sel.storage[i] & self._rdly_dq_bitslip_rst.re,
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slp = self._dly_sel.storage[i] & self._rdly_dq_bitslip.re,
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cycles = 1)
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self.submodules += dq_i_bitslip
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self.specials += Instance("IDES4_MEM",
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i_RESET = ResetSignal("sys"),
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i_PCLK = ClockSignal("sys"),
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i_FCLK = ClockSignal("sys2x"),
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i_ICLK = dqsr90,
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i_RADDR = rdpntr,
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||||
i_WADDR = wrpntr,
|
||||
i_D = dq_i,
|
||||
i_CALIB = 0,
|
||||
**{f"o_Q{n}": dq_i_bitslip.i[n] for n in range(4)},
|
||||
)
|
||||
dq_i_bitslip_o_d = Signal(4)
|
||||
self.sync += dq_i_bitslip_o_d.eq(dq_i_bitslip.o)
|
||||
self.comb += dq_i_data.eq(Cat(dq_i_bitslip_o_d, dq_i_bitslip.o))
|
||||
for n in range(8):
|
||||
self.comb += dfi.phases[n//4].rddata[n%4*databits+j].eq(dq_i_data[n])
|
||||
self.specials += Instance("IOBUF",
|
||||
i_I = dq_o,
|
||||
i_OEN = dq_o_oen,
|
||||
o_O = dq_i,
|
||||
io_IO = pads.dq[j]
|
||||
)
|
||||
|
||||
# Read Control Path ------------------------------------------------------------------------
|
||||
rdtap = cl_sys_latency - 1 + 1
|
||||
|
||||
# Creates a delay line of read commands coming from the DFI interface. The taps are used to
|
||||
# control DQS read (internal read pulse of the DQSBUF) and the output of the delay is used
|
||||
# signal a valid read data to the DFI interface.
|
||||
#
|
||||
# The DQS read must be asserted for 2 sys_clk cycles before the read data is coming back from
|
||||
# the DRAM (see 6.2.4 READ Pulse Positioning Optimization of FPGA-TN-02035-1.2)
|
||||
#
|
||||
# The read data valid is asserted for 1 sys_clk cycle when the data is available on the DFI
|
||||
# interface, the latency is the sum of the ODDRX2DQA, CAS, IDDRX2DQA latencies.
|
||||
rddata_en = TappedDelayLine(
|
||||
signal = reduce(or_, [dfi.phases[i].rddata_en for i in range(nphases)]),
|
||||
ntaps = self.settings.read_latency
|
||||
)
|
||||
self.submodules += rddata_en
|
||||
|
||||
self.comb += [phase.rddata_valid.eq(rddata_en.output) for phase in dfi.phases]
|
||||
self.comb += dqs_re.eq(rddata_en.taps[rdtap] | rddata_en.taps[rdtap + 1])
|
||||
|
||||
# Write Control Path -----------------------------------------------------------------------
|
||||
wrtap = cwl_sys_latency - 1 + 1
|
||||
|
||||
# Create a delay line of write commands coming from the DFI interface. This taps are used to
|
||||
# control DQ/DQS tristates and to select write data of the DRAM burst from the DFI interface.
|
||||
# The PHY is operating in halfrate mode (so provide 4 datas every sys_clk cycles: 2x for DDR,
|
||||
# 2x for halfrate) but DDR3 requires a burst of 8 datas (BL8) for best efficiency. Writes are
|
||||
# then performed in 2 sys_clk cycles and data needs to be selected for each cycle.
|
||||
wrdata_en = TappedDelayLine(
|
||||
signal = reduce(or_, [dfi.phases[i].wrdata_en for i in range(nphases)]),
|
||||
ntaps = wrtap + 4
|
||||
)
|
||||
self.submodules += wrdata_en
|
||||
|
||||
self.comb += dq_oe.eq(wrdata_en.taps[wrtap] | wrdata_en.taps[wrtap + 1])
|
||||
self.comb += bl8_chunk.eq(wrdata_en.taps[wrtap])
|
||||
self.comb += dqs_oe.eq(dq_oe)
|
||||
|
||||
# Write DQS Postamble/Preamble Control Path ------------------------------------------------
|
||||
# Generates DQS Preamble 1 cycle before the first write and Postamble 1 cycle after the last
|
||||
# write. During writes, DQS tristate is configured as output for at least 4 sys_clk cycles:
|
||||
# 1 for Preamble, 2 for the Write and 1 for the Postamble.
|
||||
self.comb += dqs_preamble.eq( wrdata_en.taps[wrtap - 1] & ~wrdata_en.taps[wrtap + 0])
|
||||
self.comb += dqs_postamble.eq(wrdata_en.taps[wrtap + 2] & ~wrdata_en.taps[wrtap + 1])
|
||||
Loading…
Reference in New Issue