phys: move get_cl_cw/get_sys_latency/get_sys_phases helpers to common
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@ -3,13 +3,16 @@
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# This file is Copyright (c) 2018 bunnie <bunnie@kosagi.com>
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# License: BSD
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import math
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from functools import reduce
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from operator import add
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from collections import OrderedDict
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from migen import *
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from litex.soc.interconnect import stream
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# Helpers ------------------------------------------------------------------------------------------
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burst_lengths = {
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"SDR": 1,
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@ -20,7 +23,37 @@ burst_lengths = {
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"DDR4": 8
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}
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# Settings ---------------------------------------------------------------------
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def get_cl_cw(memtype, tck):
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f_to_cl_cwl = OrderedDict()
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if memtype == "DDR2":
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f_to_cl_cwl[400e6] = (3, 2)
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f_to_cl_cwl[533e6] = (4, 3)
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f_to_cl_cwl[677e6] = (5, 4)
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f_to_cl_cwl[800e6] = (6, 5)
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f_to_cl_cwl[1066e6] = (7, 5)
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elif memtype == "DDR3":
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f_to_cl_cwl[800e6] = ( 6, 5)
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f_to_cl_cwl[1066e6] = ( 7, 6)
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f_to_cl_cwl[1333e6] = (10, 7)
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f_to_cl_cwl[1600e6] = (11, 8)
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elif memtype == "DDR4":
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f_to_cl_cwl[1600e6] = (11, 9)
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else:
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raise ValueError
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for f, (cl, cwl) in f_to_cl_cwl.items():
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if tck >= 2/f:
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return cl, cwl
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raise ValueError
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def get_sys_latency(nphases, cas_latency):
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return math.ceil(cas_latency/nphases)
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def get_sys_phases(nphases, sys_latency, cas_latency):
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dat_phase = sys_latency*nphases - cas_latency
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cmd_phase = (dat_phase - 1)%nphases
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return cmd_phase, dat_phase
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# Settings -----------------------------------------------------------------------------------------
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class Settings:
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def set_attributes(self, attributes):
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@ -56,7 +89,7 @@ class TimingSettings(Settings):
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def __init__(self, tRP, tRCD, tWR, tWTR, tREFI, tRFC, tFAW, tCCD, tRRD, tRC, tRAS, tZQCS):
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self.set_attributes(locals())
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# Layouts/Interface ------------------------------------------------------------
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# Layouts/Interface --------------------------------------------------------------------------------
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def cmd_layout(address_width):
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return [
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@ -123,7 +156,7 @@ class LiteDRAMInterface(Record):
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layout += data_layout(self.data_width)
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Record.__init__(self, layout)
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# Ports ------------------------------------------------------------------------
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# Ports --------------------------------------------------------------------------------------------
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class LiteDRAMNativePort(Settings):
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def __init__(self, mode, address_width, data_width, clock_domain="sys", id=0):
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@ -167,7 +200,7 @@ class LiteDRAMNativeReadPort(LiteDRAMNativePort):
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LiteDRAMNativePort.__init__(self, "read", *args, **kwargs)
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# Timing Controllers -----------------------------------------------------------
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# Timing Controllers -------------------------------------------------------------------------------
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class tXXDController(Module):
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def __init__(self, txxd):
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@ -6,7 +6,6 @@
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# DDR3: 800 MT/s
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import math
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from collections import OrderedDict
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from migen import *
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from migen.genlib.misc import timeline, BitSlip
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@ -16,30 +15,9 @@ from migen.genlib.misc import WaitTimer
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from litex.soc.interconnect.csr import *
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from litedram.common import PhySettings
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from litedram.common import *
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from litedram.phy.dfi import *
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# Helpers ------------------------------------------------------------------------------------------
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def get_cl_cw(memtype, tck):
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f_to_cl_cwl = OrderedDict()
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if memtype == "DDR3":
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f_to_cl_cwl[800e6] = (6, 5)
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else:
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raise ValueError
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for f, (cl, cwl) in f_to_cl_cwl.items():
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if tck >= 2/f:
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return cl, cwl
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raise ValueError
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def get_sys_latency(nphases, cas_latency):
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return math.ceil(cas_latency/nphases)
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def get_sys_phases(nphases, sys_latency, cas_latency):
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dat_phase = sys_latency*nphases - cas_latency
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cmd_phase = (dat_phase - 1)%nphases
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return cmd_phase, dat_phase
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# Lattice ECP5 DDR PHY Initialization --------------------------------------------------------------
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class ECP5DDRPHYInit(Module):
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@ -7,45 +7,16 @@
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# DDR3: 800, 1066, 1333 and 1600 MT/s
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import math
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from collections import OrderedDict
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from migen import *
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from migen.genlib.misc import BitSlip
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from litex.soc.interconnect.csr import *
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from litedram.common import PhySettings
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from litedram.common import *
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from litedram.phy.dfi import *
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def get_cl_cw(memtype, tck):
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f_to_cl_cwl = OrderedDict()
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if memtype == "DDR2":
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f_to_cl_cwl[400e6] = (3, 2)
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f_to_cl_cwl[533e6] = (4, 3)
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f_to_cl_cwl[677e6] = (5, 4)
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f_to_cl_cwl[800e6] = (6, 5)
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f_to_cl_cwl[1066e6] = (7, 5)
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elif memtype == "DDR3":
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f_to_cl_cwl[800e6] = ( 6, 5)
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f_to_cl_cwl[1066e6] = ( 7, 6)
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f_to_cl_cwl[1333e6] = (10, 7)
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f_to_cl_cwl[1600e6] = (11, 8)
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else:
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raise ValueError
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for f, (cl, cwl) in f_to_cl_cwl.items():
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if tck >= 2/f:
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return cl, cwl
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raise ValueError
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def get_sys_latency(nphases, cas_latency):
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return math.ceil(cas_latency/nphases)
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def get_sys_phases(nphases, sys_latency, cas_latency):
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dat_phase = sys_latency*nphases - cas_latency
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cmd_phase = (dat_phase - 1)%nphases
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return cmd_phase, dat_phase
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class S7DDRPHY(Module, AutoCSR):
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def __init__(self, pads, with_odelay, memtype="DDR3", nphases=4, sys_clk_freq=100e6, iodelay_clk_freq=200e6, cmd_latency=0):
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assert not (memtype == "DDR3" and nphases == 2) # FIXME: Needs BL8 support for nphases=2
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@ -6,42 +6,16 @@
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# DDR4: 1600 MT/s
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import math
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from collections import OrderedDict
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from migen import *
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from migen.genlib.misc import BitSlip, WaitTimer
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from litex.soc.interconnect.csr import *
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from litedram.common import PhySettings
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from litedram.common import *
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from litedram.phy.dfi import *
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def get_cl_cw(memtype, tck):
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f_to_cl_cwl = OrderedDict()
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if memtype == "DDR3":
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f_to_cl_cwl[800e6] = ( 6, 5)
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f_to_cl_cwl[1066e6] = ( 7, 6)
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f_to_cl_cwl[1333e6] = (10, 7)
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f_to_cl_cwl[1600e6] = (11, 8)
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elif memtype == "DDR4":
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f_to_cl_cwl[1600e6] = (11, 9)
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else:
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raise ValueError
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for f, (cl, cwl) in f_to_cl_cwl.items():
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if tck >= 2/f:
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return cl, cwl
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raise ValueError
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def get_sys_latency(nphases, cas_latency):
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return math.ceil(cas_latency/nphases)
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def get_sys_phases(nphases, sys_latency, cas_latency):
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dat_phase = sys_latency*nphases - cas_latency
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cmd_phase = (dat_phase - 1)%nphases
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return cmd_phase, dat_phase
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class DDR4DFIMux(Module):
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def __init__(self, dfi_i, dfi_o):
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for i in range(len(dfi_i.phases)):
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