README: update

README

@@ -16,13 +16,7 @@ LiteDRAM is part of LiteX libraries whose aims are to lower entry level of
 complex FPGA cores by providing simple, elegant and efficient implementations
 of components used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
 
-Since Python is used to describe the HDL, the core is highly and easily
-configurable.
-
-LiteDRAM is built using LiteX and uses technologies developed in partnership with
-M-Labs Ltd:
- - Migen enables generating HDL with Python in an efficient way.
- - MiSoC provides the basic blocks to build a powerful and small footprint SoC.
+Using Migen to describe the HDL allows the core to be highly and easily configurable.
 
 LiteDRAM can be used as LiteX library or can be integrated with your standard
 design flow by generating the verilog rtl that you will use as a standard core.
@@ -73,7 +67,7 @@ enjoy-digital.fr.
   python3 setup.py develop
   cd ..
 
-3. TODO: add/describe example design(s)
+3. TODO: add/describe examples
 
 [> Tests
 --------

setup.py

@@ -31,6 +31,6 @@ setup(
         "Operating System :: OS Independent",
         "Programming Language :: Python",
     ],
-    packages=find_packages(exclude=("test*", "sim*", "doc*", "example_designs*")),
+    packages=find_packages(exclude=("test*", "sim*", "doc*", "examples*")),
     include_package_data=True,
 )