core/refresher: rename RefreshGenerator to RefreshSequencer and simplify

This commit is contained in:
Florent Kermarrec 2019-08-14 08:07:10 +02:00
parent 8573c22cc1
commit de38b52eb6
2 changed files with 17 additions and 26 deletions

View file

@ -12,7 +12,7 @@ from litex.soc.interconnect import stream
from litedram.core.multiplexer import *
class RefreshGenerator(Module):
class RefreshSequencer(Module):
def __init__(self, cmd, trp, trfc):
self.start = Signal()
self.done = Signal()
@ -31,24 +31,15 @@ class RefreshGenerator(Module):
# Wait start
timeline(self.start, [
# Precharge all
(0, [
cmd.ras.eq(1),
cmd.we.eq(1)
]),
# Wait tRP then Auto Refresh
(trp, [
cmd.cas.eq(1),
cmd.ras.eq(1)
]),
# Wait tRFC then done
(trp + trfc, [
self.done.eq(1)
])
(0, [cmd.ras.eq(1), cmd.we.eq(1)]),
# Auto Refresh after tRP
(trp, [cmd.cas.eq(1), cmd.ras.eq(1)]),
# Done after tRP + tRFC
(trp + trfc, [self.done.eq(1)])
])
]
class RefreshTimer(Module):
def __init__(self, trefi):
self.wait = wait = Signal()
@ -91,9 +82,9 @@ class Refresher(Module):
self.comb += self.timer.reset.eq(~settings.with_refresh)
self.comb += self.timer.wait.eq(~self.timer.done)
# Refresh sequence generator
generator = RefreshGenerator(cmd, settings.timing.tRP, settings.timing.tRFC)
self.submodules.generator = generator
# Refresh sequencer
sequencer = RefreshSequencer(cmd, settings.timing.tRP, settings.timing.tRFC)
self.submodules.sequencer = sequencer
# Refresh control FSM
self.submodules.fsm = fsm = FSM()
@ -105,12 +96,12 @@ class Refresher(Module):
fsm.act("WAIT_GRANT",
cmd.valid.eq(1),
If(cmd.ready,
generator.start.eq(1),
sequencer.start.eq(1),
NextState("WAIT_SEQ")
)
)
fsm.act("WAIT_SEQ",
If(generator.done,
If(sequencer.done,
cmd.last.eq(1),
NextState("IDLE")
).Else(

View file

@ -6,14 +6,14 @@ import unittest
from migen import *
from litedram.core.multiplexer import cmd_request_rw_layout
from litedram.core.refresher import RefreshGenerator, RefreshTimer, Refresher
from litedram.core.refresher import RefreshSequencer, RefreshTimer, Refresher
def c2bool(c):
return {"-": 1, "_": 0}[c]
class TestRefresh(unittest.TestCase):
def refresh_generator_test(self, trp, trfc, starts, dones, cmds):
def refresh_sequencer_test(self, trp, trfc, starts, dones, cmds):
cmd = Record(cmd_request_rw_layout(a=16, ba=3))
def generator(dut):
dut.errors = 0
@ -26,11 +26,11 @@ class TestRefresh(unittest.TestCase):
dut.errors += 1
if (yield cmd.ras) != c2bool(ras):
dut.errors += 1
dut = RefreshGenerator(cmd, trp, trfc)
dut = RefreshSequencer(cmd, trp, trfc)
run_simulation(dut, [generator(dut)])
self.assertEqual(dut.errors, 0)
def test_refresh_generator(self):
def test_refresh_sequencer(self):
trp = 1
trfc = 2
class Obj: pass
@ -39,7 +39,7 @@ class TestRefresh(unittest.TestCase):
cmds.cas = "___-____________"
cmds.ras = "__--____________"
dones = "_____-__________"
self.refresh_generator_test(trp, trfc, starts, dones, cmds)
self.refresh_sequencer_test(trp, trfc, starts, dones, cmds)
def refresh_timer_test(self, trefi):
def generator(dut):
@ -70,7 +70,7 @@ class TestRefresh(unittest.TestCase):
class Obj: pass
settings = Obj()
settings.with_refresh = True
settings.timing =Obj()
settings.timing = Obj()
settings.timing.tREFI = 64
settings.timing.tRP = 1
settings.timing.tRFC = 2