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core/refresher: rename RefreshGenerator to RefreshSequencer and simplify
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parent
8573c22cc1
commit
de38b52eb6
2 changed files with 17 additions and 26 deletions
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@ -12,7 +12,7 @@ from litex.soc.interconnect import stream
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from litedram.core.multiplexer import *
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class RefreshGenerator(Module):
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class RefreshSequencer(Module):
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def __init__(self, cmd, trp, trfc):
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self.start = Signal()
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self.done = Signal()
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@ -31,24 +31,15 @@ class RefreshGenerator(Module):
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# Wait start
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timeline(self.start, [
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# Precharge all
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(0, [
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cmd.ras.eq(1),
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cmd.we.eq(1)
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]),
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# Wait tRP then Auto Refresh
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(trp, [
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cmd.cas.eq(1),
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cmd.ras.eq(1)
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]),
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# Wait tRFC then done
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(trp + trfc, [
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self.done.eq(1)
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])
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(0, [cmd.ras.eq(1), cmd.we.eq(1)]),
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# Auto Refresh after tRP
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(trp, [cmd.cas.eq(1), cmd.ras.eq(1)]),
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# Done after tRP + tRFC
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(trp + trfc, [self.done.eq(1)])
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])
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]
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class RefreshTimer(Module):
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def __init__(self, trefi):
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self.wait = wait = Signal()
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@ -91,9 +82,9 @@ class Refresher(Module):
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self.comb += self.timer.reset.eq(~settings.with_refresh)
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self.comb += self.timer.wait.eq(~self.timer.done)
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# Refresh sequence generator
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generator = RefreshGenerator(cmd, settings.timing.tRP, settings.timing.tRFC)
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self.submodules.generator = generator
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# Refresh sequencer
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sequencer = RefreshSequencer(cmd, settings.timing.tRP, settings.timing.tRFC)
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self.submodules.sequencer = sequencer
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# Refresh control FSM
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self.submodules.fsm = fsm = FSM()
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@ -105,12 +96,12 @@ class Refresher(Module):
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fsm.act("WAIT_GRANT",
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cmd.valid.eq(1),
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If(cmd.ready,
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generator.start.eq(1),
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sequencer.start.eq(1),
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NextState("WAIT_SEQ")
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)
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)
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fsm.act("WAIT_SEQ",
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If(generator.done,
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If(sequencer.done,
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cmd.last.eq(1),
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NextState("IDLE")
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).Else(
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@ -6,14 +6,14 @@ import unittest
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from migen import *
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from litedram.core.multiplexer import cmd_request_rw_layout
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from litedram.core.refresher import RefreshGenerator, RefreshTimer, Refresher
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from litedram.core.refresher import RefreshSequencer, RefreshTimer, Refresher
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def c2bool(c):
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return {"-": 1, "_": 0}[c]
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class TestRefresh(unittest.TestCase):
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def refresh_generator_test(self, trp, trfc, starts, dones, cmds):
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def refresh_sequencer_test(self, trp, trfc, starts, dones, cmds):
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cmd = Record(cmd_request_rw_layout(a=16, ba=3))
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def generator(dut):
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dut.errors = 0
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@ -26,11 +26,11 @@ class TestRefresh(unittest.TestCase):
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dut.errors += 1
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if (yield cmd.ras) != c2bool(ras):
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dut.errors += 1
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dut = RefreshGenerator(cmd, trp, trfc)
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dut = RefreshSequencer(cmd, trp, trfc)
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run_simulation(dut, [generator(dut)])
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self.assertEqual(dut.errors, 0)
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def test_refresh_generator(self):
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def test_refresh_sequencer(self):
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trp = 1
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trfc = 2
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class Obj: pass
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@ -39,7 +39,7 @@ class TestRefresh(unittest.TestCase):
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cmds.cas = "___-____________"
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cmds.ras = "__--____________"
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dones = "_____-__________"
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self.refresh_generator_test(trp, trfc, starts, dones, cmds)
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self.refresh_sequencer_test(trp, trfc, starts, dones, cmds)
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def refresh_timer_test(self, trefi):
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def generator(dut):
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@ -70,7 +70,7 @@ class TestRefresh(unittest.TestCase):
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class Obj: pass
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settings = Obj()
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settings.with_refresh = True
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settings.timing =Obj()
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settings.timing = Obj()
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settings.timing.tREFI = 64
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settings.timing.tRP = 1
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settings.timing.tRFC = 2
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